Re: [PATCH v2 3/8] cxl: refactor cxl_hdm_decode_init()

[Jonathan Cameron <Jonathan.Cameron@Huawei.com>]

On Mon, 09 Jan 2023 14:43:26 -0700
Dave Jiang <dave.jiang@intel.com> wrote:

> With the previous refactoring of DVSEC range registers out of
> cxl_hdm_decode_init(), it basically becomes a skeleton function. Squash
> __cxl_hdm_decode_init() with cxl_hdm_decode_init() to simplify the code.
> cxl_hdm_decode_init() now returns more error codes than just -EBUSY.
> 
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>

One trivial style comment.  Either way

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

>  int cxl_dvsec_rr_decode(struct pci_dev *pdev, int d,
>  			struct cxl_endpoint_dvsec_info *info)
>  {
> @@ -449,17 +375,68 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm,
>  {
>  	struct pci_dev *pdev = to_pci_dev(cxlds->dev);
>  	struct device *dev = &pdev->dev;
> +	void __iomem *hdm = cxlhdm->regs.hdm_decoder;
> +	struct cxl_port *port = cxlhdm->port;
> +	struct cxl_port *root;
> +	int i, rc, allowed;
> +	u32 global_ctrl;
> +
> +	global_ctrl = readl(hdm + CXL_HDM_DECODER_CTRL_OFFSET);
>  
>  	/*
> -	 * If DVSEC ranges are being used instead of HDM decoder registers there
> -	 * is no use in trying to manage those.
> +	 * If the HDM Decoder Capability is already enabled then assume
> +	 * that some other agent like platform firmware set it up.
>  	 */
> -	if (!__cxl_hdm_decode_init(cxlds, cxlhdm, info)) {
> -		dev_err(dev,
> -			"Legacy range registers configuration prevents HDM operation.\n");
> -		return -EBUSY;
> +	if (global_ctrl & CXL_HDM_DECODER_ENABLE)
> +		return devm_cxl_enable_mem(&port->dev, cxlds);
> +
> +	root = to_cxl_port(port->dev.parent);
> +	while (!is_cxl_root(root) && is_cxl_port(root->dev.parent))
> +		root = to_cxl_port(root->dev.parent);
> +	if (!is_cxl_root(root)) {
> +		dev_err(dev, "Failed to acquire root port for HDM enable\n");
> +		return -ENODEV;
> +	}
> +
> +	for (i = 0, allowed = 0; info->mem_enabled && i < info->ranges; i++) {
> +		struct device *cxld_dev;
> +
> +		cxld_dev = device_find_child(&root->dev, &info->dvsec_range[i],
> +					     dvsec_range_allowed);
> +		if (!cxld_dev) {
> +			dev_dbg(dev, "DVSEC Range%d denied by platform\n", i);
> +			continue;
> +		}
> +		dev_dbg(dev, "DVSEC Range%d allowed by platform\n", i);
> +		put_device(cxld_dev);
> +		allowed++;
>  	}
>  
> +	if (!allowed) {
> +		cxl_set_mem_enable(cxlds, 0);
> +		info->mem_enabled = 0;
> +	}
> +
> +	/*
> +	 * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base
> +	 * [High,Low] when HDM operation is enabled the range register values
> +	 * are ignored by the device, but the spec also recommends matching the
> +	 * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges
> +	 * are expected even though Linux does not require or maintain that
> +	 * match. If at least one DVSEC range is enabled and allowed, skip HDM
> +	 * Decoder Capability Enable.
> +	 */
> +	if (info->mem_enabled)
> +		return -EBUSY;
> +
> +	rc = devm_cxl_enable_hdm(&port->dev, cxlhdm);
> +	if (rc)
> +		return rc;
> +
> +	rc = devm_cxl_enable_mem(&port->dev, cxlds);
> +	if (rc)
> +		return rc;
> +
>  	return 0;

Maybe simplify to
	return devm_cxl_enable_mem(...);
if not touched again in later patches.

>  }
>  EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL);
> 
>