Re: [PATCH v2 1/8] cxl: break out range register decoding from cxl_hdm_decode_init()

[Dave Jiang <dave.jiang@intel.com>]

On 1/13/23 6:36 AM, Jonathan Cameron wrote:
> On Mon, 09 Jan 2023 14:43:09 -0700
> Dave Jiang <dave.jiang@intel.com> wrote:
> 
>> There are 2 scenarios that requires additional handling. 1. A device that
>> has active ranges in DVSEC range registers (RR) but no HDM decoder register
>> block. 2. A device that has both RR active and HDM, but the HDM decoders
>> are not programmed. The goal is to create emulated decoder software structs
>> based on the RR.
>>
>> Move the CXL DVSEC range register decoding code block from
>> cxl_hdm_decode_init() to its own function. Refactor code in preparation for
>> the HDM decoder emulation.  There is no functionality change to the code.
>> Name the new function to cxl_dvsec_rr_decode().
>>
>> The only change is to set range->start and range->end to CXL_RESOURCE_NONE
>> and skipping the reading of base registers if the range size is 0, which
>> equates to range not active.
>>
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>>
>> ---
>>
>> v2:
>> - Refactor to return when size is 0. (Jonathan)
> I think you continue rather than return when size is 0 unless I'm looking in the
> wrong place.

Yes. I think I was looking at the wrong place.

> 
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> 
>> ---
>>   drivers/cxl/core/pci.c |   63 ++++++++++++++++++++++++++++++------------------
>>   1 file changed, 40 insertions(+), 23 deletions(-)
>>
>> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
>> index 57764e9cd19d..a8ecc6ddb3d7 100644
>> --- a/drivers/cxl/core/pci.c
>> +++ b/drivers/cxl/core/pci.c
>> @@ -141,11 +141,10 @@ int cxl_await_media_ready(struct cxl_dev_state *cxlds)
>>   }
>>   EXPORT_SYMBOL_NS_GPL(cxl_await_media_ready, CXL);
>>