From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Ira Weiny <ira.weiny@intel.com>
Cc: Ravi Kanth <mvrravikanth@gmail.com>,
Gregory Price <gregory.price@memverge.com>,
"linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>,
Sajjan Rao <sajjanr@gmail.com>
Subject: Re: Support for CXL v3.0 spec with QEMU
Date: Mon, 23 Oct 2023 14:44:24 +0100 [thread overview]
Message-ID: <20231023144424.000061f4@Huawei.com> (raw)
In-Reply-To: <6532e53ed63b0_21a97294d@iweiny-mobl.notmuch>
On Fri, 20 Oct 2023 13:38:22 -0700
Ira Weiny <ira.weiny@intel.com> wrote:
> Ravi Kanth wrote:
> > Hi Jonathan / Gregory,
> > Just wanted to touch base on below questions and if you have any
> > inputs on the same. Thanks for your help.
> >
> > Thanks
> > Ravi
> >
> > On Wed, Oct 18, 2023 at 4:00 PM Ravi Kanth <mvrravikanth@gmail.com> wrote:
> > >
> > > Hi Jonathan / Gregory,
> > >
> > > 1. Do we have the support in CXL driver to read the "Device status
> > > registers" and specifically "Event status register" section 8.2.8.3
> > > and 8.2.8.3.1?
>
> Yes the upstream driver reads this when processing the Event interrupt
> from the device. Then it uses the value to chose which logs to read.
>
> See cxl_event_thread() in the kernel source.
>
> > > 2. If an interrupt is posted by the device firmware, how will user
> > > space applications be notified ? Do we have an interface for the same
> > > in CXL driver?
>
> All events are reported through the trace infrastructure.
>
> > >
> > > If the above features are already supported in CXL driver, Can you
> > > please point us to the sample code snippets to achieve the same?
>
> ndctl has the ability to monitor these events and example C code in there.
>
> See .../cxl/event_trace.c in the ndctl project.[1]
>
> [1] https://github.com/pmem/ndctl
>
> > >
> > > Also does the switch cci function change part of the mainline?
>
> I'm not sure I parse this question but I'm also not super familiar with
> switch cci. So I'll let Jonathan answer this.
Patches posted for review only at the moment - so 6.8 at earliest given timing.
https://lore.kernel.org/all/20231016125323.18318-1-Jonathan.Cameron@huawei.com/
Main change to existing handling is that a bunch of mailbox related handling is
factored out for reuse. Otherwise, it's 'just another PCI endpoint driver'.
Jonathan
>
> Ira
>
> > >
> > > Thanks for your help in advance.
> > >
> > > Thanks
> > > Ravi
> > >
>
> [snip]
>
next prev parent reply other threads:[~2023-10-23 13:44 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-10 16:12 Support for CXL v3.0 spec with QEMU Ravi Kanth
2023-08-10 16:33 ` Jonathan Cameron
2023-08-10 16:40 ` Ravi Kanth
2023-08-11 12:04 ` Ravi Kanth
2023-08-11 13:52 ` Jonathan Cameron
2023-08-16 11:41 ` Ravi Kanth
2023-08-23 17:03 ` Jonathan Cameron
2023-09-01 14:03 ` Ravi Kanth
2023-09-01 14:18 ` Gregory Price
2023-09-01 14:37 ` Ravi Kanth
2023-09-01 16:19 ` Ravi Kanth
[not found] ` <SJ0PR17MB5512449C5FFD76AD50B3D3AF83E4A@SJ0PR17MB5512.namprd17.prod.outlook.com>
2023-09-02 14:58 ` Ravi Kanth
2023-10-18 10:30 ` Ravi Kanth
2023-10-19 17:08 ` Ravi Kanth
2023-10-20 20:38 ` Ira Weiny
2023-10-22 6:45 ` Ravi Kanth
2023-10-23 13:50 ` Jonathan Cameron
2023-10-26 1:52 ` Ravi Kanth
2023-10-26 8:59 ` Jonathan Cameron
2023-10-23 13:44 ` Jonathan Cameron [this message]
2023-08-11 13:49 ` Jonathan Cameron
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