* [ndctl PATCH] cxl/test: Add 3-way HB interleave testcase to cxl-xor-region.sh
@ 2024-02-14 7:14 alison.schofield
2024-02-14 19:28 ` Verma, Vishal L
0 siblings, 1 reply; 3+ messages in thread
From: alison.schofield @ 2024-02-14 7:14 UTC (permalink / raw)
To: Vishal Verma; +Cc: Alison Schofield, nvdimm, linux-cxl
From: Alison Schofield <alison.schofield@intel.com>
cxl-xor-region.sh includes test cases for 1 & 2 way host bridge
interleaves. Add a new test case to exercise the modulo math
function the CXL driver uses to find positions in a 3-way host
bridge interleave.
Skip this test case, don't fail, if the new 3-way XOR decoder
is not present in cxl/test.
Add the missing check_dmesg helper before exiting this test.
Signed-off-by: Alison Schofield <alison.schofield@intel.com>
---
test/cxl-xor-region.sh | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/test/cxl-xor-region.sh b/test/cxl-xor-region.sh
index 117e7a4bba61..2f3b4aa5208a 100644
--- a/test/cxl-xor-region.sh
+++ b/test/cxl-xor-region.sh
@@ -86,11 +86,44 @@ setup_x4()
memdevs="$mem0 $mem1 $mem2 $mem3"
}
+setup_x3()
+{
+ # find an x3 decoder
+ decoder=$($CXL list -b cxl_test -D -d root | jq -r ".[] |
+ select(.pmem_capable == true) |
+ select(.nr_targets == 3) |
+ .decoder")
+
+ if [[ ! $decoder ]]; then
+ echo "no x3 decoder found, skipping xor-x3 test"
+ return
+ fi
+
+ # Find a memdev for each host-bridge interleave position
+ port_dev0=$($CXL list -T -d "$decoder" | jq -r ".[] |
+ .targets | .[] | select(.position == 0) | .target")
+ port_dev1=$($CXL list -T -d "$decoder" | jq -r ".[] |
+ .targets | .[] | select(.position == 1) | .target")
+ port_dev2=$($CXL list -T -d "$decoder" | jq -r ".[] |
+ .targets | .[] | select(.position == 2) | .target")
+ mem0=$($CXL list -M -p "$port_dev0" | jq -r ".[0].memdev")
+ mem1=$($CXL list -M -p "$port_dev1" | jq -r ".[0].memdev")
+ mem2=$($CXL list -M -p "$port_dev2" | jq -r ".[0].memdev")
+ memdevs="$mem0 $mem1 $mem2"
+}
+
setup_x1
create_and_destroy_region
setup_x2
create_and_destroy_region
setup_x4
create_and_destroy_region
+# x3 decoder may not be available in cxl/test topo yet
+setup_x3
+if [[ $decoder ]]; then
+ create_and_destroy_region
+fi
+
+check_dmesg "$LINENO"
modprobe -r cxl_test
--
2.37.3
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [ndctl PATCH] cxl/test: Add 3-way HB interleave testcase to cxl-xor-region.sh
2024-02-14 7:14 [ndctl PATCH] cxl/test: Add 3-way HB interleave testcase to cxl-xor-region.sh alison.schofield
@ 2024-02-14 19:28 ` Verma, Vishal L
2024-02-14 21:49 ` Alison Schofield
0 siblings, 1 reply; 3+ messages in thread
From: Verma, Vishal L @ 2024-02-14 19:28 UTC (permalink / raw)
To: Schofield, Alison; +Cc: linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev
On Tue, 2024-02-13 at 23:14 -0800, alison.schofield@intel.com wrote:
> From: Alison Schofield <alison.schofield@intel.com>
>
> cxl-xor-region.sh includes test cases for 1 & 2 way host bridge
> interleaves. Add a new test case to exercise the modulo math
> function the CXL driver uses to find positions in a 3-way host
> bridge interleave.
>
> Skip this test case, don't fail, if the new 3-way XOR decoder
> is not present in cxl/test.
>
> Add the missing check_dmesg helper before exiting this test.
>
> Signed-off-by: Alison Schofield <alison.schofield@intel.com>
> ---
> test/cxl-xor-region.sh | 33 +++++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/test/cxl-xor-region.sh b/test/cxl-xor-region.sh
> index 117e7a4bba61..2f3b4aa5208a 100644
> --- a/test/cxl-xor-region.sh
> +++ b/test/cxl-xor-region.sh
> @@ -86,11 +86,44 @@ setup_x4()
> memdevs="$mem0 $mem1 $mem2 $mem3"
> }
>
> +setup_x3()
> +{
> + # find an x3 decoder
> + decoder=$($CXL list -b cxl_test -D -d root | jq -r ".[] |
> + select(.pmem_capable == true) |
> + select(.nr_targets == 3) |
> + .decoder")
Are these lines..
> +
> + if [[ ! $decoder ]]; then
> + echo "no x3 decoder found, skipping xor-x3 test"
> + return
> + fi
> +
> + # Find a memdev for each host-bridge interleave position
> + port_dev0=$($CXL list -T -d "$decoder" | jq -r ".[] |
> + .targets | .[] | select(.position == 0) | .target")
> + port_dev1=$($CXL list -T -d "$decoder" | jq -r ".[] |
> + .targets | .[] | select(.position == 1) | .target")
> + port_dev2=$($CXL list -T -d "$decoder" | jq -r ".[] |
> + .targets | .[] | select(.position == 2) | .target")
..and these mis-indented?
Looks good otherwise.
> + mem0=$($CXL list -M -p "$port_dev0" | jq -r ".[0].memdev")
> + mem1=$($CXL list -M -p "$port_dev1" | jq -r ".[0].memdev")
> + mem2=$($CXL list -M -p "$port_dev2" | jq -r ".[0].memdev")
> + memdevs="$mem0 $mem1 $mem2"
> +}
> +
> setup_x1
> create_and_destroy_region
> setup_x2
> create_and_destroy_region
> setup_x4
> create_and_destroy_region
> +# x3 decoder may not be available in cxl/test topo yet
> +setup_x3
> +if [[ $decoder ]]; then
> + create_and_destroy_region
> +fi
> +
> +check_dmesg "$LINENO"
>
> modprobe -r cxl_test
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [ndctl PATCH] cxl/test: Add 3-way HB interleave testcase to cxl-xor-region.sh
2024-02-14 19:28 ` Verma, Vishal L
@ 2024-02-14 21:49 ` Alison Schofield
0 siblings, 0 replies; 3+ messages in thread
From: Alison Schofield @ 2024-02-14 21:49 UTC (permalink / raw)
To: Verma, Vishal L; +Cc: linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev
On Wed, Feb 14, 2024 at 11:28:45AM -0800, Vishal Verma wrote:
> On Tue, 2024-02-13 at 23:14 -0800, alison.schofield@intel.com wrote:
> > From: Alison Schofield <alison.schofield@intel.com>
> >
> > cxl-xor-region.sh includes test cases for 1 & 2 way host bridge
> > interleaves. Add a new test case to exercise the modulo math
> > function the CXL driver uses to find positions in a 3-way host
> > bridge interleave.
> >
> > Skip this test case, don't fail, if the new 3-way XOR decoder
> > is not present in cxl/test.
> >
> > Add the missing check_dmesg helper before exiting this test.
> >
> > Signed-off-by: Alison Schofield <alison.schofield@intel.com>
> > ---
> > test/cxl-xor-region.sh | 33 +++++++++++++++++++++++++++++++++
> > 1 file changed, 33 insertions(+)
> >
> > diff --git a/test/cxl-xor-region.sh b/test/cxl-xor-region.sh
> > index 117e7a4bba61..2f3b4aa5208a 100644
> > --- a/test/cxl-xor-region.sh
> > +++ b/test/cxl-xor-region.sh
> > @@ -86,11 +86,44 @@ setup_x4()
> > memdevs="$mem0 $mem1 $mem2 $mem3"
> > }
> >
> > +setup_x3()
> > +{
> > + # find an x3 decoder
> > + decoder=$($CXL list -b cxl_test -D -d root | jq -r ".[] |
> > + select(.pmem_capable == true) |
> > + select(.nr_targets == 3) |
> > + .decoder")
>
> Are these lines..
>
> > +
> > + if [[ ! $decoder ]]; then
> > + echo "no x3 decoder found, skipping xor-x3 test"
> > + return
> > + fi
> > +
> > + # Find a memdev for each host-bridge interleave position
> > + port_dev0=$($CXL list -T -d "$decoder" | jq -r ".[] |
> > + .targets | .[] | select(.position == 0) | .target")
> > + port_dev1=$($CXL list -T -d "$decoder" | jq -r ".[] |
> > + .targets | .[] | select(.position == 1) | .target")
> > + port_dev2=$($CXL list -T -d "$decoder" | jq -r ".[] |
> > + .targets | .[] | select(.position == 2) | .target")
>
> ..and these mis-indented?
Thanks for calling it out. I'll tidy up white space in a new revision.
snip
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2024-02-14 7:14 [ndctl PATCH] cxl/test: Add 3-way HB interleave testcase to cxl-xor-region.sh alison.schofield
2024-02-14 19:28 ` Verma, Vishal L
2024-02-14 21:49 ` Alison Schofield
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