[PATCH v2] cxl/test: Define a CFMWS capable of a 3 way HB interleave

[PATCH v2] cxl/test: Define a CFMWS capable of a 3 way HB interleave

[alison.schofield]

From: Alison Schofield <alison.schofield@intel.com>

The CXL unit test cxl-xor-region.sh is skipping a 1+1+1 region
interleave test case because the window is not defined.

Additionally, upcoming expansion of 3 way HB interleave test cases
(like 2+2+2) require the same window.

Replace an unused CFMWS with a 3-way capable CFMWS in the set of
CFMWS's loaded when interleave_arithmetic=1.

Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Tested-by: Li Zhijian <lizhijian@fujitsu.com>
---

v2: Adjust target list length (Ira)

 tools/testing/cxl/test/cxl.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
index 083a66a52731..1c3336095923 100644
--- a/tools/testing/cxl/test/cxl.c
+++ b/tools/testing/cxl/test/cxl.c
@@ -155,7 +155,7 @@ static struct {
 	} cfmws7;
 	struct {
 		struct acpi_cedt_cfmws cfmws;
-		u32 target[4];
+		u32 target[3];
 	} cfmws8;
 	struct {
 		struct acpi_cedt_cxims cxims;
@@ -331,14 +331,14 @@ static struct {
 				.length = sizeof(mock_cedt.cfmws8),
 			},
 			.interleave_arithmetic = ACPI_CEDT_CFMWS_ARITHMETIC_XOR,
-			.interleave_ways = 2,
-			.granularity = 0,
+			.interleave_ways = 8,
+			.granularity = 1,
 			.restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
 					ACPI_CEDT_CFMWS_RESTRICT_PMEM,
 			.qtg_id = FAKE_QTG_ID,
-			.window_size = SZ_256M * 16UL,
+			.window_size = SZ_512M * 6UL,
 		},
-		.target = { 0, 1, 0, 1, },
+		.target = { 0, 1, 2, },
 	},
 	.cxims0 = {
 		.cxims = {

base-commit: 2bb67004903cfd35710750654669a77e7223fcd1
-- 
2.37.3

Re: [PATCH v2] cxl/test: Define a CFMWS capable of a 3 way HB interleave

[Dave Jiang]

On 2/26/25 3:19 PM, alison.schofield@intel.com wrote:
> From: Alison Schofield <alison.schofield@intel.com>
> 
> The CXL unit test cxl-xor-region.sh is skipping a 1+1+1 region
> interleave test case because the window is not defined.
> 
> Additionally, upcoming expansion of 3 way HB interleave test cases
> (like 2+2+2) require the same window.
> 
> Replace an unused CFMWS with a 3-way capable CFMWS in the set of
> CFMWS's loaded when interleave_arithmetic=1.
> 
> Signed-off-by: Alison Schofield <alison.schofield@intel.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> Reviewed-by: Ira Weiny <ira.weiny@intel.com>
> Tested-by: Li Zhijian <lizhijian@fujitsu.com>

Applied to cxl/next

> ---
> 
> v2: Adjust target list length (Ira)
> 
>  tools/testing/cxl/test/cxl.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
> index 083a66a52731..1c3336095923 100644
> --- a/tools/testing/cxl/test/cxl.c
> +++ b/tools/testing/cxl/test/cxl.c
> @@ -155,7 +155,7 @@ static struct {
>  	} cfmws7;
>  	struct {
>  		struct acpi_cedt_cfmws cfmws;
> -		u32 target[4];
> +		u32 target[3];
>  	} cfmws8;
>  	struct {
>  		struct acpi_cedt_cxims cxims;
> @@ -331,14 +331,14 @@ static struct {
>  				.length = sizeof(mock_cedt.cfmws8),
>  			},
>  			.interleave_arithmetic = ACPI_CEDT_CFMWS_ARITHMETIC_XOR,
> -			.interleave_ways = 2,
> -			.granularity = 0,
> +			.interleave_ways = 8,
> +			.granularity = 1,
>  			.restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
>  					ACPI_CEDT_CFMWS_RESTRICT_PMEM,
>  			.qtg_id = FAKE_QTG_ID,
> -			.window_size = SZ_256M * 16UL,
> +			.window_size = SZ_512M * 6UL,
>  		},
> -		.target = { 0, 1, 0, 1, },
> +		.target = { 0, 1, 2, },
>  	},
>  	.cxims0 = {
>  		.cxims = {
> 
> base-commit: 2bb67004903cfd35710750654669a77e7223fcd1