* [PATCH qemu v2 0/5] cxl: r3.2 specification event updates.
@ 2026-01-02 15:15 Jonathan Cameron
2026-01-02 15:15 ` [PATCH qemu v2 1/5] qapi: cxl: Refactor CXL event injection for common commands arguments Jonathan Cameron
` (4 more replies)
0 siblings, 5 replies; 16+ messages in thread
From: Jonathan Cameron @ 2026-01-02 15:15 UTC (permalink / raw)
To: Michael Tsirkin, qemu-devel, shiju.jose, armbru
Cc: linuxarm, linux-cxl, Ravi Shankar
Hi Michael,
This is a rebase/resend of:
https://lore.kernel.org/qemu-devel/20250917141355.293217-1-Jonathan.Cameron@huawei.com/
which I think slipped through the cracks for 10.2.
Original cover letter:
This is the 1st CXL set that I think is ready for upstream.
They are lightly tweaked and rebased from the first part of:
https://lore.kernel.org/qemu-devel/20250811085530.2263-1-shiju.jose@huawei.com/
[PATCH v6 0/8] hw/cxl: Update CXL events to rev3.2 and add maintenance support for memory repair features
I've split that series up as the two parts were only slightly connected.
The initial rework was a request from Markus from an earlier version.
Shiju Jose (5):
qapi: cxl: Refactor CXL event injection for common commands arguments
hw/cxl/events: Update for rev3.2 common event record format
hw/cxl/events: Updates for rev3.2 general media event record
hw/cxl/events: Updates for rev3.2 DRAM event record
hw/cxl/events: Updates for rev3.2 memory module event record
qapi/cxl.json | 151 +++++++++++++++++++++++++--------
include/hw/cxl/cxl_device.h | 7 +-
include/hw/cxl/cxl_events.h | 38 +++++++--
hw/cxl/cxl-events.c | 3 +-
hw/cxl/cxl-mailbox-utils.c | 3 +-
hw/mem/cxl_type3.c | 163 ++++++++++++++++++++++++++++++++++--
hw/mem/cxl_type3_stubs.c | 41 ++++++++-
7 files changed, 347 insertions(+), 59 deletions(-)
--
2.48.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH qemu v2 1/5] qapi: cxl: Refactor CXL event injection for common commands arguments
2026-01-02 15:15 [PATCH qemu v2 0/5] cxl: r3.2 specification event updates Jonathan Cameron
@ 2026-01-02 15:15 ` Jonathan Cameron
2026-01-12 12:12 ` Markus Armbruster
2026-01-02 15:15 ` [PATCH qemu v2 2/5] hw/cxl/events: Update for rev3.2 common event record format Jonathan Cameron
` (3 subsequent siblings)
4 siblings, 1 reply; 16+ messages in thread
From: Jonathan Cameron @ 2026-01-02 15:15 UTC (permalink / raw)
To: Michael Tsirkin, qemu-devel, shiju.jose, armbru
Cc: linuxarm, linux-cxl, Ravi Shankar
From: Shiju Jose <shiju.jose@huawei.com>
Refactor CXL event injection to use struct for common command
arguments.
Suggested-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
qapi/cxl.json | 89 +++++++++++++++++++++++++++++++++------------------
1 file changed, 58 insertions(+), 31 deletions(-)
diff --git a/qapi/cxl.json b/qapi/cxl.json
index eeddb58d1d..d5b86159f1 100644
--- a/qapi/cxl.json
+++ b/qapi/cxl.json
@@ -31,11 +31,10 @@
}
##
-# @cxl-inject-general-media-event:
+# @CXLCommonEventBase:
#
-# Inject an event record for a General Media Event (CXL r3.0
-# 8.2.9.2.1.1). This event type is reported via one of the event logs
-# specified via the log parameter.
+# Common event base for a CXL Event (CXL r3.0 8.2.9.2.1
+# Table 8-42 Common Event Record Format).
#
# @path: CXL type 3 device canonical QOM path
#
@@ -44,6 +43,16 @@
# @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
# Record Format, Event Record Flags for subfield definitions.
#
+# Since: 8.1
+##
+{ 'struct': 'CXLCommonEventBase',
+ 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8' } }
+
+##
+# @CXLGeneralMediaEvent:
+#
+# Event record for a General Media Event (CXL r3.0 8.2.9.2.1.1).
+#
# @dpa: Device Physical Address (relative to @path device). Note
# lower bits include some flags. See CXL r3.0 Table 8-43 General
# Media Event Record, Physical Address.
@@ -74,26 +83,29 @@
#
# Since: 8.1
##
-{ 'command': 'cxl-inject-general-media-event',
- 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8',
- 'dpa': 'uint64', 'descriptor': 'uint8',
+{ 'struct': 'CXLGeneralMediaEvent',
+ 'base': 'CXLCommonEventBase',
+ 'data': { 'dpa': 'uint64', 'descriptor': 'uint8',
'type': 'uint8', 'transaction-type': 'uint8',
'*channel': 'uint8', '*rank': 'uint8',
'*device': 'uint32', '*component-id': 'str' } }
##
-# @cxl-inject-dram-event:
-#
-# Inject an event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
-# This event type is reported via one of the event logs specified via
-# the log parameter.
+# @cxl-inject-general-media-event:
#
-# @path: CXL type 3 device canonical QOM path
+# Inject an event record for a General Media Event (CXL r3.0
+# 8.2.9.2.1.1). This event type is reported via one of the event
+# logs specified via the log parameter.
#
-# @log: Event log to add the event to
+# Since: 8.1
+##
+{ 'command': 'cxl-inject-general-media-event',
+ 'data': 'CXLGeneralMediaEvent' }
+
+##
+# @CXLDRAMEvent:
#
-# @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
-# Record Format, Event Record Flags for subfield definitions.
+# Event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
#
# @dpa: Device Physical Address (relative to @path device). Note
# lower bits include some flags. See CXL r3.0 Table 8-44 DRAM
@@ -133,9 +145,9 @@
#
# Since: 8.1
##
-{ 'command': 'cxl-inject-dram-event',
- 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8',
- 'dpa': 'uint64', 'descriptor': 'uint8',
+{ 'struct': 'CXLDRAMEvent',
+ 'base': 'CXLCommonEventBase',
+ 'data': { 'dpa': 'uint64', 'descriptor': 'uint8',
'type': 'uint8', 'transaction-type': 'uint8',
'*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32',
'*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32',
@@ -143,18 +155,21 @@
}}
##
-# @cxl-inject-memory-module-event:
+# @cxl-inject-dram-event:
#
-# Inject an event record for a Memory Module Event (CXL r3.0
-# 8.2.9.2.1.3). This event includes a copy of the Device Health info
-# at the time of the event.
+# Inject an event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
+# This event type is reported via one of the event logs
+# specified via the log parameter.
#
-# @path: CXL type 3 device canonical QOM path
+# Since: 8.1
+##
+{ 'command': 'cxl-inject-dram-event',
+ 'data': 'CXLDRAMEvent' }
+
+##
+# @CXLMemModuleEvent:
#
-# @log: Event Log to add the event to
-#
-# @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
-# Record Format, Event Record Flags for subfield definitions.
+# Event record for a Memory Module Event (CXL r3.0 8.2.9.2.1.3).
#
# @type: Device Event Type. See CXL r3.0 Table 8-45 Memory Module
# Event Record for bit definitions for bit definiions.
@@ -185,9 +200,9 @@
#
# Since: 8.1
##
-{ 'command': 'cxl-inject-memory-module-event',
- 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags' : 'uint8',
- 'type': 'uint8', 'health-status': 'uint8',
+{ 'struct': 'CXLMemModuleEvent',
+ 'base': 'CXLCommonEventBase',
+ 'data': { 'type': 'uint8', 'health-status': 'uint8',
'media-status': 'uint8', 'additional-status': 'uint8',
'life-used': 'uint8', 'temperature' : 'int16',
'dirty-shutdown-count': 'uint32',
@@ -195,6 +210,18 @@
'corrected-persistent-error-count': 'uint32'
}}
+##
+# @cxl-inject-memory-module-event:
+#
+# Inject an event record for a DRAM Event (CXL r3.0 8.2.9.2.1.3)
+# This event type is reported via one of the event logs
+# specified via the log parameter.
+#
+# Since: 8.1
+##
+{ 'command': 'cxl-inject-memory-module-event',
+ 'data': 'CXLMemModuleEvent' }
+
##
# @cxl-inject-poison:
#
--
2.48.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH qemu v2 2/5] hw/cxl/events: Update for rev3.2 common event record format
2026-01-02 15:15 [PATCH qemu v2 0/5] cxl: r3.2 specification event updates Jonathan Cameron
2026-01-02 15:15 ` [PATCH qemu v2 1/5] qapi: cxl: Refactor CXL event injection for common commands arguments Jonathan Cameron
@ 2026-01-02 15:15 ` Jonathan Cameron
2026-01-12 12:16 ` Markus Armbruster
2026-01-02 15:15 ` [PATCH qemu v2 3/5] hw/cxl/events: Updates for rev3.2 general media event record Jonathan Cameron
` (2 subsequent siblings)
4 siblings, 1 reply; 16+ messages in thread
From: Jonathan Cameron @ 2026-01-02 15:15 UTC (permalink / raw)
To: Michael Tsirkin, qemu-devel, shiju.jose, armbru
Cc: linuxarm, linux-cxl, Ravi Shankar
From: Shiju Jose <shiju.jose@huawei.com>
CXL spec 3.2 section 8.2.9.2.1 Table 8-55, Common Event Record
format has updated with optional Maintenance Operation Subclass,
LD ID and ID of the device head information.
Add updates for the above optional parameters in the related
CXL events reporting and in the QMP commands to inject CXL events.
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
qapi/cxl.json | 20 ++++++++---
include/hw/cxl/cxl_device.h | 7 +++-
include/hw/cxl/cxl_events.h | 15 ++++++--
hw/cxl/cxl-events.c | 3 +-
hw/cxl/cxl-mailbox-utils.c | 3 +-
hw/mem/cxl_type3.c | 70 ++++++++++++++++++++++++++++++++-----
hw/mem/cxl_type3_stubs.c | 24 +++++++++++--
7 files changed, 121 insertions(+), 21 deletions(-)
diff --git a/qapi/cxl.json b/qapi/cxl.json
index d5b86159f1..b3c2ac9575 100644
--- a/qapi/cxl.json
+++ b/qapi/cxl.json
@@ -33,20 +33,32 @@
##
# @CXLCommonEventBase:
#
-# Common event base for a CXL Event (CXL r3.0 8.2.9.2.1
-# Table 8-42 Common Event Record Format).
+# Common event base for a CXL Event (CXL r3.2 8.2.10.2.1
+# Table 8-55 Common Event Record Format).
#
# @path: CXL type 3 device canonical QOM path
#
# @log: event log to add the event to
#
-# @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
+# @flags: Event Record Flags. See CXL r3.2 Table 8-55 Common Event
# Record Format, Event Record Flags for subfield definitions.
#
+# @maint-op-class: Maintenance operation class the device requests to
+# initiate.
+#
+# @maint-op-subclass: Maintenance operation subclass the device
+# requests to initiate.
+#
+# @ld-id: LD ID of LD from where the event originated.
+#
+# @head-id: ID of the device head from where the event originated.
+#
# Since: 8.1
##
{ 'struct': 'CXLCommonEventBase',
- 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8' } }
+ 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint32',
+ '*maint-op-class':'uint8', '*maint-op-subclass':'uint8',
+ '*ld-id':'uint16', '*head-id':'uint8' } }
##
# @CXLGeneralMediaEvent:
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index 165355baf9..e461a824b6 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -723,7 +723,12 @@ bool ct3_test_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa,
uint64_t len);
void cxl_assign_event_header(CXLEventRecordHdr *hdr,
const QemuUUID *uuid, uint32_t flags,
- uint8_t length, uint64_t timestamp);
+ uint8_t length, uint64_t timestamp,
+ bool has_maint_op_class, uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id);
void cxl_create_dc_event_records_for_extents(CXLType3Dev *ct3d,
CXLDCEventType type,
CXLDCExtentRaw extents[],
diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h
index 758b075a64..4d9cfdb621 100644
--- a/include/hw/cxl/cxl_events.h
+++ b/include/hw/cxl/cxl_events.h
@@ -29,9 +29,15 @@ typedef enum CXLEventLogType {
/*
* Common Event Record Format
- * CXL r3.1 section 8.2.9.2.1: Event Records; Table 8-43
+ * CXL r3.2 section 8.2.10.2.1: Event Records; Table 8-55
*/
-#define CXL_EVENT_REC_HDR_RES_LEN 0xf
+#define CXL_EVENT_REC_FLAGS_PERMANENT_COND BIT(2)
+#define CXL_EVENT_REC_FLAGS_MAINT_NEEDED BIT(3)
+#define CXL_EVENT_REC_FLAGS_PERF_DEGRADED BIT(4)
+#define CXL_EVENT_REC_FLAGS_HW_REPLACEMENT_NEEDED BIT(5)
+#define CXL_EVENT_REC_FLAGS_MAINT_OP_SUBCLASS_VALID BIT(6)
+#define CXL_EVENT_REC_FLAGS_LD_ID_VALID BIT(7)
+#define CXL_EVENT_REC_FLAGS_HEAD_ID_VALID BIT(8)
typedef struct CXLEventRecordHdr {
QemuUUID id;
uint8_t length;
@@ -40,7 +46,10 @@ typedef struct CXLEventRecordHdr {
uint16_t related_handle;
uint64_t timestamp;
uint8_t maint_op_class;
- uint8_t reserved[CXL_EVENT_REC_HDR_RES_LEN];
+ uint8_t maint_op_subclass;
+ uint16_t ld_id;
+ uint8_t head_id;
+ uint8_t reserved[0xb];
} QEMU_PACKED CXLEventRecordHdr;
#define CXL_EVENT_RECORD_DATA_LENGTH 0x50
diff --git a/hw/cxl/cxl-events.c b/hw/cxl/cxl-events.c
index 7583dd9162..5356dfb5b3 100644
--- a/hw/cxl/cxl-events.c
+++ b/hw/cxl/cxl-events.c
@@ -271,7 +271,8 @@ void cxl_create_dc_event_records_for_extents(CXLType3Dev *ct3d,
&dynamic_capacity_uuid,
(1 << CXL_EVENT_TYPE_INFO),
sizeof(event_rec),
- cxl_device_get_timestamp(&ct3d->cxl_dstate));
+ cxl_device_get_timestamp(&ct3d->cxl_dstate),
+ 0, 0, 0, 0, 0, 0, 0, 0);
event_rec.type = type;
event_rec.validity_flags = 1;
event_rec.host_id = 0;
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index 6cfdd98168..e9528da70c 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -3458,7 +3458,8 @@ static CXLRetCode cmd_fm_set_dc_region_config(const struct cxl_cmd *cmd,
&dynamic_capacity_uuid,
(1 << CXL_EVENT_TYPE_INFO),
sizeof(dcEvent),
- cxl_device_get_timestamp(&ct3d->cxl_dstate));
+ cxl_device_get_timestamp(&ct3d->cxl_dstate),
+ 0, 0, 0, 0, 0, 0, 0, 0);
dcEvent.type = DC_EVENT_REGION_CONFIG_UPDATED;
dcEvent.validity_flags = 1;
dcEvent.host_id = 0;
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 6eb20137a0..371bd4dc6a 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -1592,12 +1592,39 @@ void qmp_cxl_inject_correctable_error(const char *path, CxlCorErrorType type,
void cxl_assign_event_header(CXLEventRecordHdr *hdr,
const QemuUUID *uuid, uint32_t flags,
- uint8_t length, uint64_t timestamp)
+ uint8_t length, uint64_t timestamp,
+ bool has_maint_op_class, uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id)
{
- st24_le_p(&hdr->flags, flags);
hdr->length = length;
memcpy(&hdr->id, uuid, sizeof(hdr->id));
stq_le_p(&hdr->timestamp, timestamp);
+
+ if (has_maint_op_class) {
+ hdr->maint_op_class = maint_op_class;
+ } else {
+ hdr->maint_op_class = 0;
+ }
+
+ if (has_maint_op_subclass) {
+ flags |= CXL_EVENT_REC_FLAGS_MAINT_OP_SUBCLASS_VALID;
+ hdr->maint_op_subclass = maint_op_subclass;
+ }
+
+ if (has_ld_id) {
+ flags |= CXL_EVENT_REC_FLAGS_LD_ID_VALID;
+ stw_le_p(&hdr->ld_id, ld_id);
+ }
+
+ if (has_head_id) {
+ flags |= CXL_EVENT_REC_FLAGS_HEAD_ID_VALID;
+ hdr->head_id = head_id;
+ }
+
+ st24_le_p(&hdr->flags, flags);
}
static const QemuUUID gen_media_uuid = {
@@ -1637,7 +1664,13 @@ static int ct3d_qmp_cxl_event_log_enc(CxlEventLog log)
}
/* Component ID is device specific. Define this as a string. */
void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
- uint8_t flags, uint64_t dpa,
+ uint32_t flags, bool has_maint_op_class,
+ uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id,
+ uint64_t dpa,
uint8_t descriptor, uint8_t type,
uint8_t transaction_type,
bool has_channel, uint8_t channel,
@@ -1675,7 +1708,10 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
memset(&gem, 0, sizeof(gem));
cxl_assign_event_header(hdr, &gen_media_uuid, flags, sizeof(gem),
- cxl_device_get_timestamp(&ct3d->cxl_dstate));
+ cxl_device_get_timestamp(&ct3d->cxl_dstate),
+ has_maint_op_class, maint_op_class,
+ has_maint_op_subclass, maint_op_subclass,
+ has_ld_id, ld_id, has_head_id, head_id);
stq_le_p(&gem.phys_addr, dpa);
gem.descriptor = descriptor;
@@ -1719,7 +1755,13 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
#define CXL_DRAM_VALID_COLUMN BIT(6)
#define CXL_DRAM_VALID_CORRECTION_MASK BIT(7)
-void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
+void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
+ uint32_t flags,
+ bool has_maint_op_class, uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id,
uint64_t dpa, uint8_t descriptor,
uint8_t type, uint8_t transaction_type,
bool has_channel, uint8_t channel,
@@ -1762,7 +1804,10 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
memset(&dram, 0, sizeof(dram));
cxl_assign_event_header(hdr, &dram_uuid, flags, sizeof(dram),
- cxl_device_get_timestamp(&ct3d->cxl_dstate));
+ cxl_device_get_timestamp(&ct3d->cxl_dstate),
+ has_maint_op_class, maint_op_class,
+ has_maint_op_subclass, maint_op_subclass,
+ has_ld_id, ld_id, has_head_id, head_id);
stq_le_p(&dram.phys_addr, dpa);
dram.descriptor = descriptor;
dram.type = type;
@@ -1822,7 +1867,13 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
}
void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
- uint8_t flags, uint8_t type,
+ uint32_t flags, bool has_maint_op_class,
+ uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id,
+ uint8_t type,
uint8_t health_status,
uint8_t media_status,
uint8_t additional_status,
@@ -1861,7 +1912,10 @@ void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
memset(&module, 0, sizeof(module));
cxl_assign_event_header(hdr, &memory_module_uuid, flags, sizeof(module),
- cxl_device_get_timestamp(&ct3d->cxl_dstate));
+ cxl_device_get_timestamp(&ct3d->cxl_dstate),
+ has_maint_op_class, maint_op_class,
+ has_maint_op_subclass, maint_op_subclass,
+ has_ld_id, ld_id, has_head_id, head_id);
module.type = type;
module.health_status = health_status;
diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c
index c1a5e4a7c1..91b1478114 100644
--- a/hw/mem/cxl_type3_stubs.c
+++ b/hw/mem/cxl_type3_stubs.c
@@ -14,7 +14,13 @@
#include "qapi/qapi-commands-cxl.h"
void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
- uint8_t flags, uint64_t dpa,
+ uint32_t flags, bool has_maint_op_class,
+ uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id,
+ uint64_t dpa,
uint8_t descriptor, uint8_t type,
uint8_t transaction_type,
bool has_channel, uint8_t channel,
@@ -23,7 +29,13 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
const char *component_id,
Error **errp) {}
-void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
+void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
+ uint32_t flags,
+ bool has_maint_op_class, uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id,
uint64_t dpa, uint8_t descriptor,
uint8_t type, uint8_t transaction_type,
bool has_channel, uint8_t channel,
@@ -38,7 +50,13 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
Error **errp) {}
void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
- uint8_t flags, uint8_t type,
+ uint32_t flags, bool has_maint_op_class,
+ uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id,
+ uint8_t type,
uint8_t health_status,
uint8_t media_status,
uint8_t additional_status,
--
2.48.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH qemu v2 3/5] hw/cxl/events: Updates for rev3.2 general media event record
2026-01-02 15:15 [PATCH qemu v2 0/5] cxl: r3.2 specification event updates Jonathan Cameron
2026-01-02 15:15 ` [PATCH qemu v2 1/5] qapi: cxl: Refactor CXL event injection for common commands arguments Jonathan Cameron
2026-01-02 15:15 ` [PATCH qemu v2 2/5] hw/cxl/events: Update for rev3.2 common event record format Jonathan Cameron
@ 2026-01-02 15:15 ` Jonathan Cameron
2026-01-12 12:18 ` Markus Armbruster
2026-01-02 15:15 ` [PATCH qemu v2 4/5] hw/cxl/events: Updates for rev3.2 DRAM " Jonathan Cameron
2026-01-02 15:15 ` [PATCH qemu v2 5/5] hw/cxl/events: Updates for rev3.2 memory module " Jonathan Cameron
4 siblings, 1 reply; 16+ messages in thread
From: Jonathan Cameron @ 2026-01-02 15:15 UTC (permalink / raw)
To: Michael Tsirkin, qemu-devel, shiju.jose, armbru
Cc: linuxarm, linux-cxl, Ravi Shankar
From: Shiju Jose <shiju.jose@huawei.com>
CXL spec rev3.2 section 8.2.10.2.1.1 Table 8-57, general media event
table has updated with following new fields.
1. Advanced Programmable Corrected Memory Error Threshold Event Flags
2. Corrected Memory Error Count at Event
3. Memory Event Sub-Type
4. Support for component ID in the PLDM format.
Add updates for the above spec changes in the CXL general media event
reporting and QMP command to inject general media event.
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
qapi/cxl.json | 15 ++++++++++++++-
include/hw/cxl/cxl_events.h | 7 +++++--
hw/mem/cxl_type3.c | 29 +++++++++++++++++++++++++++++
hw/mem/cxl_type3_stubs.c | 6 ++++++
4 files changed, 54 insertions(+), 3 deletions(-)
diff --git a/qapi/cxl.json b/qapi/cxl.json
index b3c2ac9575..c5ecbe9646 100644
--- a/qapi/cxl.json
+++ b/qapi/cxl.json
@@ -93,6 +93,16 @@
# @component-id: Device specific component identifier for the event.
# May describe a field replaceable sub-component of the device.
#
+# @is-comp-id-pldm: This flag specifies whether the device-specific
+# component identifier format follows PLDM.
+#
+# @cme-ev-flags: Advanced programmable corrected memory error
+# threshold event flags.
+#
+# @cme-count: Corrected memory error count at event.
+#
+# @sub-type: Memory event sub-type.
+#
# Since: 8.1
##
{ 'struct': 'CXLGeneralMediaEvent',
@@ -100,7 +110,10 @@
'data': { 'dpa': 'uint64', 'descriptor': 'uint8',
'type': 'uint8', 'transaction-type': 'uint8',
'*channel': 'uint8', '*rank': 'uint8',
- '*device': 'uint32', '*component-id': 'str' } }
+ '*device': 'uint32', '*component-id': 'str',
+ '*is-comp-id-pldm':'bool',
+ '*cme-ev-flags':'uint8', '*cme-count':'uint32',
+ 'sub-type':'uint8' } }
##
# @cxl-inject-general-media-event:
diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h
index 4d9cfdb621..352f9891bd 100644
--- a/include/hw/cxl/cxl_events.h
+++ b/include/hw/cxl/cxl_events.h
@@ -115,10 +115,10 @@ typedef struct CXLEventInterruptPolicy {
/*
* General Media Event Record
- * CXL r3.1 Section 8.2.9.2.1.1; Table 8-45
+ * CXL r3.2 Section 8.2.10.2.1.1; Table 8-57
*/
#define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10
-#define CXL_EVENT_GEN_MED_RES_SIZE 0x2e
+#define CXL_EVENT_GEN_MED_RES_SIZE 0x29
typedef struct CXLEventGenMedia {
CXLEventRecordHdr hdr;
uint64_t phys_addr;
@@ -130,6 +130,9 @@ typedef struct CXLEventGenMedia {
uint8_t rank;
uint8_t device[3];
uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
+ uint8_t cme_ev_flags;
+ uint8_t cme_count[3];
+ uint8_t sub_type;
uint8_t reserved[CXL_EVENT_GEN_MED_RES_SIZE];
} QEMU_PACKED CXLEventGenMedia;
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 371bd4dc6a..d03a9f0edc 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -1646,6 +1646,11 @@ static const QemuUUID memory_module_uuid = {
#define CXL_GMER_VALID_RANK BIT(1)
#define CXL_GMER_VALID_DEVICE BIT(2)
#define CXL_GMER_VALID_COMPONENT BIT(3)
+#define CXL_GMER_VALID_COMPONENT_ID_FORMAT BIT(4)
+
+#define CXL_GMER_EV_DESC_UCE BIT(0)
+#define CXL_GMER_EV_DESC_THRESHOLD_EVENT BIT(1)
+#define CXL_GMER_EV_DESC_POISON_LIST_OVERFLOW_EVENT BIT(2)
static int ct3d_qmp_cxl_event_log_enc(CxlEventLog log)
{
@@ -1677,6 +1682,12 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
bool has_rank, uint8_t rank,
bool has_device, uint32_t device,
const char *component_id,
+ bool has_comp_id_pldm,
+ bool is_comp_id_pldm,
+ bool has_cme_ev_flags,
+ uint8_t cme_ev_flags,
+ bool has_cme_count, uint32_t cme_count,
+ uint8_t sub_type,
Error **errp)
{
Object *obj = object_resolve_path(path, NULL);
@@ -1737,10 +1748,28 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
strncpy((char *)gem.component_id, component_id,
sizeof(gem.component_id) - 1);
valid_flags |= CXL_GMER_VALID_COMPONENT;
+ if (has_comp_id_pldm && is_comp_id_pldm) {
+ valid_flags |= CXL_GMER_VALID_COMPONENT_ID_FORMAT;
+ }
}
stw_le_p(&gem.validity_flags, valid_flags);
+ if (has_cme_ev_flags) {
+ gem.cme_ev_flags = cme_ev_flags;
+ } else {
+ gem.cme_ev_flags = 0;
+ }
+
+ if (has_cme_count) {
+ descriptor |= CXL_GMER_EV_DESC_THRESHOLD_EVENT;
+ st24_le_p(gem.cme_count, cme_count);
+ } else {
+ st24_le_p(gem.cme_count, 0);
+ }
+
+ gem.sub_type = sub_type;
+
if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&gem)) {
cxl_event_irq_assert(ct3d);
}
diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c
index 91b1478114..2047e97846 100644
--- a/hw/mem/cxl_type3_stubs.c
+++ b/hw/mem/cxl_type3_stubs.c
@@ -27,6 +27,12 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
bool has_rank, uint8_t rank,
bool has_device, uint32_t device,
const char *component_id,
+ bool has_comp_id_pldm,
+ bool is_comp_id_pldm,
+ bool has_cme_ev_flags,
+ uint8_t cme_ev_flags,
+ bool has_cme_count, uint32_t cme_count,
+ uint8_t sub_type,
Error **errp) {}
void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
--
2.48.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH qemu v2 4/5] hw/cxl/events: Updates for rev3.2 DRAM event record
2026-01-02 15:15 [PATCH qemu v2 0/5] cxl: r3.2 specification event updates Jonathan Cameron
` (2 preceding siblings ...)
2026-01-02 15:15 ` [PATCH qemu v2 3/5] hw/cxl/events: Updates for rev3.2 general media event record Jonathan Cameron
@ 2026-01-02 15:15 ` Jonathan Cameron
2026-01-12 12:19 ` Markus Armbruster
2026-01-02 15:15 ` [PATCH qemu v2 5/5] hw/cxl/events: Updates for rev3.2 memory module " Jonathan Cameron
4 siblings, 1 reply; 16+ messages in thread
From: Jonathan Cameron @ 2026-01-02 15:15 UTC (permalink / raw)
To: Michael Tsirkin, qemu-devel, shiju.jose, armbru
Cc: linuxarm, linux-cxl, Ravi Shankar
From: Shiju Jose <shiju.jose@huawei.com>
CXL spec rev3.2 section 8.2.10.2.1.2 Table 8-58, DRAM event record
has updated with following new fields.
1. Component Identifier
2. Sub-channel of the memory event location
3. Advanced Programmable Corrected Memory Error Threshold Event Flags
4. Corrected Volatile Memory Error Count at Event
5. Memory Event Sub-Type
Add updates for the above spec changes in the CXL DRAM event
reporting and QMP command to inject DRAM event.
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
qapi/cxl.json | 21 ++++++++++++++++++-
include/hw/cxl/cxl_events.h | 9 ++++++--
hw/mem/cxl_type3.c | 42 +++++++++++++++++++++++++++++++++++++
hw/mem/cxl_type3_stubs.c | 7 +++++++
4 files changed, 76 insertions(+), 3 deletions(-)
diff --git a/qapi/cxl.json b/qapi/cxl.json
index c5ecbe9646..3e4bad4ad0 100644
--- a/qapi/cxl.json
+++ b/qapi/cxl.json
@@ -168,6 +168,21 @@
# @correction-mask: Bits within each nibble. Used in order of bits
# set in the nibble-mask. Up to 4 nibbles may be covered.
#
+# @component-id: Device specific component identifier for the event.
+# May describe a field replaceable sub-component of the device.
+#
+# @is-comp-id-pldm: This flag specifies whether the device-specific
+# component identifier format follows PLDM.
+#
+# @sub-channel: The sub-channel of the memory event location.
+#
+# @cme-ev-flags: Advanced programmable corrected memory error
+# threshold event flags.
+#
+# @cvme-count: Corrected volatile memory error count at event.
+#
+# @sub-type: Memory event sub-type.
+#
# Since: 8.1
##
{ 'struct': 'CXLDRAMEvent',
@@ -176,7 +191,11 @@
'type': 'uint8', 'transaction-type': 'uint8',
'*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32',
'*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32',
- '*column': 'uint16', '*correction-mask': [ 'uint64' ]
+ '*column': 'uint16', '*correction-mask': [ 'uint64' ],
+ '*component-id': 'str', '*is-comp-id-pldm':'bool',
+ '*sub-channel':'uint8',
+ '*cme-ev-flags':'uint8', '*cvme-count':'uint32',
+ 'sub-type':'uint8'
}}
##
diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h
index 352f9891bd..a3c5f2ec20 100644
--- a/include/hw/cxl/cxl_events.h
+++ b/include/hw/cxl/cxl_events.h
@@ -138,7 +138,7 @@ typedef struct CXLEventGenMedia {
/*
* DRAM Event Record
- * CXL r3.1 Section 8.2.9.2.1.2: Table 8-46
+ * CXL r3.2 Section 8.2.10.2.1.2: Table 8-58
* All fields little endian.
*/
typedef struct CXLEventDram {
@@ -156,7 +156,12 @@ typedef struct CXLEventDram {
uint8_t row[3];
uint16_t column;
uint64_t correction_mask[4];
- uint8_t reserved[0x17];
+ uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
+ uint8_t sub_channel;
+ uint8_t cme_ev_flags;
+ uint8_t cvme_count[3];
+ uint8_t sub_type;
+ uint8_t reserved;
} QEMU_PACKED CXLEventDram;
/*
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index d03a9f0edc..3da538bafb 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -1783,6 +1783,13 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
#define CXL_DRAM_VALID_ROW BIT(5)
#define CXL_DRAM_VALID_COLUMN BIT(6)
#define CXL_DRAM_VALID_CORRECTION_MASK BIT(7)
+#define CXL_DRAM_VALID_COMPONENT BIT(8)
+#define CXL_DRAM_VALID_COMPONENT_ID_FORMAT BIT(9)
+#define CXL_DRAM_VALID_SUB_CHANNEL BIT(10)
+
+#define CXL_DRAM_EV_DESC_UCE BIT(0)
+#define CXL_DRAM_EV_DESC_THRESHOLD_EVENT BIT(1)
+#define CXL_DRAM_EV_DESC_POISON_LIST_OVERFLOW_EVENT BIT(2)
void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
uint32_t flags,
@@ -1802,6 +1809,12 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
bool has_column, uint16_t column,
bool has_correction_mask,
uint64List *correction_mask,
+ const char *component_id,
+ bool has_comp_id_pldm, bool is_comp_id_pldm,
+ bool has_sub_channel, uint8_t sub_channel,
+ bool has_cme_ev_flags, uint8_t cme_ev_flags,
+ bool has_cvme_count, uint32_t cvme_count,
+ uint8_t sub_type,
Error **errp)
{
Object *obj = object_resolve_path(path, NULL);
@@ -1888,6 +1901,35 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
valid_flags |= CXL_DRAM_VALID_CORRECTION_MASK;
}
+ if (component_id) {
+ strncpy((char *)dram.component_id, component_id,
+ sizeof(dram.component_id) - 1);
+ valid_flags |= CXL_DRAM_VALID_COMPONENT;
+ if (has_comp_id_pldm && is_comp_id_pldm) {
+ valid_flags |= CXL_DRAM_VALID_COMPONENT_ID_FORMAT;
+ }
+ }
+
+ if (has_sub_channel) {
+ dram.sub_channel = sub_channel;
+ valid_flags |= CXL_DRAM_VALID_SUB_CHANNEL;
+ }
+
+ if (has_cme_ev_flags) {
+ dram.cme_ev_flags = cme_ev_flags;
+ } else {
+ dram.cme_ev_flags = 0;
+ }
+
+ if (has_cvme_count) {
+ descriptor |= CXL_DRAM_EV_DESC_THRESHOLD_EVENT;
+ st24_le_p(dram.cvme_count, cvme_count);
+ } else {
+ st24_le_p(dram.cvme_count, 0);
+ }
+
+ dram.sub_type = sub_type;
+
stw_le_p(&dram.validity_flags, valid_flags);
if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&dram)) {
diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c
index 2047e97846..231dda263f 100644
--- a/hw/mem/cxl_type3_stubs.c
+++ b/hw/mem/cxl_type3_stubs.c
@@ -53,6 +53,13 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
bool has_column, uint16_t column,
bool has_correction_mask,
uint64List *correction_mask,
+ const char *component_id,
+ bool has_comp_id_pldm,
+ bool is_comp_id_pldm,
+ bool has_sub_channel, uint8_t sub_channel,
+ bool has_cme_ev_flags, uint8_t cme_ev_flags,
+ bool has_cvme_count, uint32_t cvme_count,
+ uint8_t sub_type,
Error **errp) {}
void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
--
2.48.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH qemu v2 5/5] hw/cxl/events: Updates for rev3.2 memory module event record
2026-01-02 15:15 [PATCH qemu v2 0/5] cxl: r3.2 specification event updates Jonathan Cameron
` (3 preceding siblings ...)
2026-01-02 15:15 ` [PATCH qemu v2 4/5] hw/cxl/events: Updates for rev3.2 DRAM " Jonathan Cameron
@ 2026-01-02 15:15 ` Jonathan Cameron
2026-01-12 12:20 ` Markus Armbruster
2026-01-12 12:23 ` Markus Armbruster
4 siblings, 2 replies; 16+ messages in thread
From: Jonathan Cameron @ 2026-01-02 15:15 UTC (permalink / raw)
To: Michael Tsirkin, qemu-devel, shiju.jose, armbru
Cc: linuxarm, linux-cxl, Ravi Shankar
From: Shiju Jose <shiju.jose@huawei.com>
CXL spec rev3.2 section 8.2.10.2.1.3 Table 8-50, memory module
event record has updated with following new fields.
1. Validity Flags
2. Component Identifier
3. Device Event Sub-Type
Add updates for the above spec changes in the CXL memory module
event reporting and QMP command to inject memory module event.
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
qapi/cxl.json | 12 +++++++++++-
include/hw/cxl/cxl_events.h | 7 +++++--
hw/mem/cxl_type3.c | 20 ++++++++++++++++++++
hw/mem/cxl_type3_stubs.c | 4 ++++
4 files changed, 40 insertions(+), 3 deletions(-)
diff --git a/qapi/cxl.json b/qapi/cxl.json
index 3e4bad4ad0..752d46cda2 100644
--- a/qapi/cxl.json
+++ b/qapi/cxl.json
@@ -242,6 +242,14 @@
# @corrected-persistent-error-count: Total number of correctable
# errors in persistent memory
#
+# @component-id: Device specific component identifier for the event.
+# May describe a field replaceable sub-component of the device.
+#
+# @is-comp-id-pldm: This flag specifies whether the device-specific
+# component identifier format follows PLDM.
+#
+# @sub-type: Device event sub-type.
+#
# Since: 8.1
##
{ 'struct': 'CXLMemModuleEvent',
@@ -251,7 +259,9 @@
'life-used': 'uint8', 'temperature' : 'int16',
'dirty-shutdown-count': 'uint32',
'corrected-volatile-error-count': 'uint32',
- 'corrected-persistent-error-count': 'uint32'
+ 'corrected-persistent-error-count': 'uint32',
+ '*component-id': 'str', '*is-comp-id-pldm':'bool',
+ 'sub-type':'uint8'
}}
##
diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h
index a3c5f2ec20..4a7836ad72 100644
--- a/include/hw/cxl/cxl_events.h
+++ b/include/hw/cxl/cxl_events.h
@@ -166,7 +166,7 @@ typedef struct CXLEventDram {
/*
* Memory Module Event Record
- * CXL r3.1 Section 8.2.9.2.1.3: Table 8-47
+ * CXL r3.2 Section 8.2.10.2.1.3: Table 8-59
* All fields little endian.
*/
typedef struct CXLEventMemoryModule {
@@ -180,7 +180,10 @@ typedef struct CXLEventMemoryModule {
uint32_t dirty_shutdown_count;
uint32_t corrected_volatile_error_count;
uint32_t corrected_persistent_error_count;
- uint8_t reserved[0x3d];
+ uint16_t validity_flags;
+ uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
+ uint8_t sub_type;
+ uint8_t reserved[0x2a];
} QEMU_PACKED CXLEventMemoryModule;
/*
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 3da538bafb..4dc9b223f4 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -1937,6 +1937,9 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
}
}
+#define CXL_MMER_VALID_COMPONENT BIT(0)
+#define CXL_MMER_VALID_COMPONENT_ID_FORMAT BIT(1)
+
void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
uint32_t flags, bool has_maint_op_class,
uint8_t maint_op_class,
@@ -1953,11 +1956,16 @@ void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
uint32_t dirty_shutdown_count,
uint32_t corrected_volatile_error_count,
uint32_t corrected_persist_error_count,
+ const char *component_id,
+ bool has_comp_id_pldm,
+ bool is_comp_id_pldm,
+ uint8_t sub_type,
Error **errp)
{
Object *obj = object_resolve_path(path, NULL);
CXLEventMemoryModule module;
CXLEventRecordHdr *hdr = &module.hdr;
+ uint16_t valid_flags = 0;
CXLDeviceState *cxlds;
CXLType3Dev *ct3d;
uint8_t enc_log;
@@ -2000,6 +2008,18 @@ void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
stl_le_p(&module.corrected_persistent_error_count,
corrected_persist_error_count);
+ if (component_id) {
+ strncpy((char *)module.component_id, component_id,
+ sizeof(module.component_id) - 1);
+ valid_flags |= CXL_MMER_VALID_COMPONENT;
+ if (has_comp_id_pldm && is_comp_id_pldm) {
+ valid_flags |= CXL_MMER_VALID_COMPONENT_ID_FORMAT;
+ }
+ }
+ module.sub_type = sub_type;
+
+ stw_le_p(&module.validity_flags, valid_flags);
+
if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&module)) {
cxl_event_irq_assert(ct3d);
}
diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c
index 231dda263f..98292a931c 100644
--- a/hw/mem/cxl_type3_stubs.c
+++ b/hw/mem/cxl_type3_stubs.c
@@ -78,6 +78,10 @@ void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
uint32_t dirty_shutdown_count,
uint32_t corrected_volatile_error_count,
uint32_t corrected_persist_error_count,
+ const char *component_id,
+ bool has_comp_id_pldm,
+ bool is_comp_id_pldm,
+ uint8_t sub_type,
Error **errp) {}
void qmp_cxl_inject_poison(const char *path, uint64_t start, uint64_t length,
--
2.48.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH qemu v2 1/5] qapi: cxl: Refactor CXL event injection for common commands arguments
2026-01-02 15:15 ` [PATCH qemu v2 1/5] qapi: cxl: Refactor CXL event injection for common commands arguments Jonathan Cameron
@ 2026-01-12 12:12 ` Markus Armbruster
0 siblings, 0 replies; 16+ messages in thread
From: Markus Armbruster @ 2026-01-12 12:12 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Michael Tsirkin, qemu-devel, shiju.jose, linuxarm, linux-cxl,
Ravi Shankar
Jonathan Cameron <Jonathan.Cameron@huawei.com> writes:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> Refactor CXL event injection to use struct for common command
> arguments.
>
> Suggested-by: Markus Armbruster <armbru@redhat.com>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
I verified this does not change the external interface by comparing
generated qapi-introspect.c before and after.
> ---
> qapi/cxl.json | 89 +++++++++++++++++++++++++++++++++------------------
> 1 file changed, 58 insertions(+), 31 deletions(-)
>
> diff --git a/qapi/cxl.json b/qapi/cxl.json
> index eeddb58d1d..d5b86159f1 100644
> --- a/qapi/cxl.json
> +++ b/qapi/cxl.json
> @@ -31,11 +31,10 @@
> }
>
> ##
> -# @cxl-inject-general-media-event:
> +# @CXLCommonEventBase:
> #
> -# Inject an event record for a General Media Event (CXL r3.0
> -# 8.2.9.2.1.1). This event type is reported via one of the event logs
> -# specified via the log parameter.
> +# Common event base for a CXL Event (CXL r3.0 8.2.9.2.1
> +# Table 8-42 Common Event Record Format).
> #
> # @path: CXL type 3 device canonical QOM path
> #
> @@ -44,6 +43,16 @@
> # @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
> # Record Format, Event Record Flags for subfield definitions.
> #
> +# Since: 8.1
> +##
> +{ 'struct': 'CXLCommonEventBase',
> + 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8' } }
> +
> +##
> +# @CXLGeneralMediaEvent:
> +#
> +# Event record for a General Media Event (CXL r3.0 8.2.9.2.1.1).
> +#
> # @dpa: Device Physical Address (relative to @path device). Note
> # lower bits include some flags. See CXL r3.0 Table 8-43 General
> # Media Event Record, Physical Address.
> @@ -74,26 +83,29 @@
> #
> # Since: 8.1
> ##
> -{ 'command': 'cxl-inject-general-media-event',
> - 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8',
> - 'dpa': 'uint64', 'descriptor': 'uint8',
> +{ 'struct': 'CXLGeneralMediaEvent',
> + 'base': 'CXLCommonEventBase',
> + 'data': { 'dpa': 'uint64', 'descriptor': 'uint8',
> 'type': 'uint8', 'transaction-type': 'uint8',
> '*channel': 'uint8', '*rank': 'uint8',
> '*device': 'uint32', '*component-id': 'str' } }
>
> ##
> -# @cxl-inject-dram-event:
> -#
> -# Inject an event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
> -# This event type is reported via one of the event logs specified via
> -# the log parameter.
> +# @cxl-inject-general-media-event:
> #
> -# @path: CXL type 3 device canonical QOM path
> +# Inject an event record for a General Media Event (CXL r3.0
> +# 8.2.9.2.1.1). This event type is reported via one of the event
> +# logs specified via the log parameter.
> #
> -# @log: Event log to add the event to
> +# Since: 8.1
> +##
> +{ 'command': 'cxl-inject-general-media-event',
> + 'data': 'CXLGeneralMediaEvent' }
> +
> +##
> +# @CXLDRAMEvent:
> #
> -# @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
> -# Record Format, Event Record Flags for subfield definitions.
> +# Event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
> #
> # @dpa: Device Physical Address (relative to @path device). Note
> # lower bits include some flags. See CXL r3.0 Table 8-44 DRAM
> @@ -133,9 +145,9 @@
> #
> # Since: 8.1
> ##
> -{ 'command': 'cxl-inject-dram-event',
> - 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8',
> - 'dpa': 'uint64', 'descriptor': 'uint8',
> +{ 'struct': 'CXLDRAMEvent',
> + 'base': 'CXLCommonEventBase',
> + 'data': { 'dpa': 'uint64', 'descriptor': 'uint8',
> 'type': 'uint8', 'transaction-type': 'uint8',
> '*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32',
> '*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32',
> @@ -143,18 +155,21 @@
> }}
>
> ##
> -# @cxl-inject-memory-module-event:
> +# @cxl-inject-dram-event:
> #
> -# Inject an event record for a Memory Module Event (CXL r3.0
> -# 8.2.9.2.1.3). This event includes a copy of the Device Health info
> -# at the time of the event.
> +# Inject an event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
> +# This event type is reported via one of the event logs
> +# specified via the log parameter.
> #
> -# @path: CXL type 3 device canonical QOM path
> +# Since: 8.1
> +##
> +{ 'command': 'cxl-inject-dram-event',
> + 'data': 'CXLDRAMEvent' }
> +
> +##
> +# @CXLMemModuleEvent:
> #
> -# @log: Event Log to add the event to
> -#
> -# @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
> -# Record Format, Event Record Flags for subfield definitions.
> +# Event record for a Memory Module Event (CXL r3.0 8.2.9.2.1.3).
> #
> # @type: Device Event Type. See CXL r3.0 Table 8-45 Memory Module
> # Event Record for bit definitions for bit definiions.
> @@ -185,9 +200,9 @@
> #
> # Since: 8.1
> ##
> -{ 'command': 'cxl-inject-memory-module-event',
> - 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags' : 'uint8',
> - 'type': 'uint8', 'health-status': 'uint8',
> +{ 'struct': 'CXLMemModuleEvent',
> + 'base': 'CXLCommonEventBase',
> + 'data': { 'type': 'uint8', 'health-status': 'uint8',
> 'media-status': 'uint8', 'additional-status': 'uint8',
> 'life-used': 'uint8', 'temperature' : 'int16',
> 'dirty-shutdown-count': 'uint32',
> @@ -195,6 +210,18 @@
> 'corrected-persistent-error-count': 'uint32'
> }}
>
> +##
> +# @cxl-inject-memory-module-event:
> +#
> +# Inject an event record for a DRAM Event (CXL r3.0 8.2.9.2.1.3)
> +# This event type is reported via one of the event logs
> +# specified via the log parameter.
I believe this should be
# Inject an event record for a Memory Module Event (CXL r3.0
# 8.2.9.2.1.3). This event includes a copy of the Device Health info
# at the time of the event.
> +#
> +# Since: 8.1
> +##
> +{ 'command': 'cxl-inject-memory-module-event',
> + 'data': 'CXLMemModuleEvent' }
> +
> ##
> # @cxl-inject-poison:
> #
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH qemu v2 2/5] hw/cxl/events: Update for rev3.2 common event record format
2026-01-02 15:15 ` [PATCH qemu v2 2/5] hw/cxl/events: Update for rev3.2 common event record format Jonathan Cameron
@ 2026-01-12 12:16 ` Markus Armbruster
2026-01-13 17:47 ` Jonathan Cameron
0 siblings, 1 reply; 16+ messages in thread
From: Markus Armbruster @ 2026-01-12 12:16 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Michael Tsirkin, qemu-devel, shiju.jose, linuxarm, linux-cxl,
Ravi Shankar
Jonathan Cameron <Jonathan.Cameron@huawei.com> writes:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> CXL spec 3.2 section 8.2.9.2.1 Table 8-55, Common Event Record
> format has updated with optional Maintenance Operation Subclass,
> LD ID and ID of the device head information.
>
> Add updates for the above optional parameters in the related
> CXL events reporting and in the QMP commands to inject CXL events.
>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> qapi/cxl.json | 20 ++++++++---
> include/hw/cxl/cxl_device.h | 7 +++-
> include/hw/cxl/cxl_events.h | 15 ++++++--
> hw/cxl/cxl-events.c | 3 +-
> hw/cxl/cxl-mailbox-utils.c | 3 +-
> hw/mem/cxl_type3.c | 70 ++++++++++++++++++++++++++++++++-----
> hw/mem/cxl_type3_stubs.c | 24 +++++++++++--
> 7 files changed, 121 insertions(+), 21 deletions(-)
>
> diff --git a/qapi/cxl.json b/qapi/cxl.json
> index d5b86159f1..b3c2ac9575 100644
> --- a/qapi/cxl.json
> +++ b/qapi/cxl.json
> @@ -33,20 +33,32 @@
> ##
> # @CXLCommonEventBase:
> #
> -# Common event base for a CXL Event (CXL r3.0 8.2.9.2.1
> -# Table 8-42 Common Event Record Format).
> +# Common event base for a CXL Event (CXL r3.2 8.2.10.2.1
> +# Table 8-55 Common Event Record Format).
> #
> # @path: CXL type 3 device canonical QOM path
> #
> # @log: event log to add the event to
> #
> -# @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
> +# @flags: Event Record Flags. See CXL r3.2 Table 8-55 Common Event
> # Record Format, Event Record Flags for subfield definitions.
> #
> +# @maint-op-class: Maintenance operation class the device requests to
> +# initiate.
> +#
> +# @maint-op-subclass: Maintenance operation subclass the device
> +# requests to initiate.
> +#
> +# @ld-id: LD ID of LD from where the event originated.
What's an LD?
> +#
> +# @head-id: ID of the device head from where the event originated.
Are these identifiers taken from the CXL spec?
> +#
> # Since: 8.1
> ##
> { 'struct': 'CXLCommonEventBase',
> - 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8' } }
> + 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint32',
> + '*maint-op-class':'uint8', '*maint-op-subclass':'uint8',
> + '*ld-id':'uint16', '*head-id':'uint8' } }
>
> ##
> # @CXLGeneralMediaEvent:
[...]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH qemu v2 3/5] hw/cxl/events: Updates for rev3.2 general media event record
2026-01-02 15:15 ` [PATCH qemu v2 3/5] hw/cxl/events: Updates for rev3.2 general media event record Jonathan Cameron
@ 2026-01-12 12:18 ` Markus Armbruster
0 siblings, 0 replies; 16+ messages in thread
From: Markus Armbruster @ 2026-01-12 12:18 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Michael Tsirkin, qemu-devel, shiju.jose, linuxarm, linux-cxl,
Ravi Shankar
Jonathan Cameron <Jonathan.Cameron@huawei.com> writes:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> CXL spec rev3.2 section 8.2.10.2.1.1 Table 8-57, general media event
> table has updated with following new fields.
> 1. Advanced Programmable Corrected Memory Error Threshold Event Flags
> 2. Corrected Memory Error Count at Event
> 3. Memory Event Sub-Type
> 4. Support for component ID in the PLDM format.
>
> Add updates for the above spec changes in the CXL general media event
> reporting and QMP command to inject general media event.
>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> qapi/cxl.json | 15 ++++++++++++++-
> include/hw/cxl/cxl_events.h | 7 +++++--
> hw/mem/cxl_type3.c | 29 +++++++++++++++++++++++++++++
> hw/mem/cxl_type3_stubs.c | 6 ++++++
> 4 files changed, 54 insertions(+), 3 deletions(-)
>
> diff --git a/qapi/cxl.json b/qapi/cxl.json
> index b3c2ac9575..c5ecbe9646 100644
> --- a/qapi/cxl.json
> +++ b/qapi/cxl.json
> @@ -93,6 +93,16 @@
##
# @CXLGeneralMediaEvent:
#
# Event record for a General Media Event (CXL r3.0 8.2.9.2.1.1).
#
# @dpa: Device Physical Address (relative to @path device). Note
# lower bits include some flags. See CXL r3.0 Table 8-43 General
# Media Event Record, Physical Address.
#
[...]
> # @component-id: Device specific component identifier for the event.
> # May describe a field replaceable sub-component of the device.
> #
> +# @is-comp-id-pldm: This flag specifies whether the device-specific
> +# component identifier format follows PLDM.
> +#
> +# @cme-ev-flags: Advanced programmable corrected memory error
> +# threshold event flags.
> +#
> +# @cme-count: Corrected memory error count at event.
> +#
> +# @sub-type: Memory event sub-type.
> +#
You're not updating the reference to the CXL spec from 3.0 to 3.2.
Intentional?
> # Since: 8.1
> ##
> { 'struct': 'CXLGeneralMediaEvent',
> @@ -100,7 +110,10 @@
> 'data': { 'dpa': 'uint64', 'descriptor': 'uint8',
> 'type': 'uint8', 'transaction-type': 'uint8',
> '*channel': 'uint8', '*rank': 'uint8',
> - '*device': 'uint32', '*component-id': 'str' } }
> + '*device': 'uint32', '*component-id': 'str',
> + '*is-comp-id-pldm':'bool',
> + '*cme-ev-flags':'uint8', '*cme-count':'uint32',
> + 'sub-type':'uint8' } }
>
> ##
> # @cxl-inject-general-media-event:
[...]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH qemu v2 4/5] hw/cxl/events: Updates for rev3.2 DRAM event record
2026-01-02 15:15 ` [PATCH qemu v2 4/5] hw/cxl/events: Updates for rev3.2 DRAM " Jonathan Cameron
@ 2026-01-12 12:19 ` Markus Armbruster
0 siblings, 0 replies; 16+ messages in thread
From: Markus Armbruster @ 2026-01-12 12:19 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Michael Tsirkin, qemu-devel, shiju.jose, armbru, linuxarm,
linux-cxl, Ravi Shankar
Jonathan Cameron <Jonathan.Cameron@huawei.com> writes:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> CXL spec rev3.2 section 8.2.10.2.1.2 Table 8-58, DRAM event record
> has updated with following new fields.
> 1. Component Identifier
> 2. Sub-channel of the memory event location
> 3. Advanced Programmable Corrected Memory Error Threshold Event Flags
> 4. Corrected Volatile Memory Error Count at Event
> 5. Memory Event Sub-Type
>
> Add updates for the above spec changes in the CXL DRAM event
> reporting and QMP command to inject DRAM event.
>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> qapi/cxl.json | 21 ++++++++++++++++++-
> include/hw/cxl/cxl_events.h | 9 ++++++--
> hw/mem/cxl_type3.c | 42 +++++++++++++++++++++++++++++++++++++
> hw/mem/cxl_type3_stubs.c | 7 +++++++
> 4 files changed, 76 insertions(+), 3 deletions(-)
>
> diff --git a/qapi/cxl.json b/qapi/cxl.json
> index c5ecbe9646..3e4bad4ad0 100644
> --- a/qapi/cxl.json
> +++ b/qapi/cxl.json
> @@ -168,6 +168,21 @@
##
# @CXLDRAMEvent:
#
# Event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
#
# @dpa: Device Physical Address (relative to @path device). Note
# lower bits include some flags. See CXL r3.0 Table 8-44 DRAM
# Event Record, Physical Address.
#
[...]
> # @correction-mask: Bits within each nibble. Used in order of bits
> # set in the nibble-mask. Up to 4 nibbles may be covered.
> #
> +# @component-id: Device specific component identifier for the event.
> +# May describe a field replaceable sub-component of the device.
> +#
> +# @is-comp-id-pldm: This flag specifies whether the device-specific
> +# component identifier format follows PLDM.
> +#
> +# @sub-channel: The sub-channel of the memory event location.
> +#
> +# @cme-ev-flags: Advanced programmable corrected memory error
> +# threshold event flags.
> +#
> +# @cvme-count: Corrected volatile memory error count at event.
> +#
> +# @sub-type: Memory event sub-type.
> +#
You're not updating the reference to the CXL spec from 3.0 to 3.2.
Intentional?
> # Since: 8.1
> ##
> { 'struct': 'CXLDRAMEvent',
> @@ -176,7 +191,11 @@
> 'type': 'uint8', 'transaction-type': 'uint8',
> '*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32',
> '*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32',
> - '*column': 'uint16', '*correction-mask': [ 'uint64' ]
> + '*column': 'uint16', '*correction-mask': [ 'uint64' ],
> + '*component-id': 'str', '*is-comp-id-pldm':'bool',
> + '*sub-channel':'uint8',
> + '*cme-ev-flags':'uint8', '*cvme-count':'uint32',
> + 'sub-type':'uint8'
> }}
>
> ##
[...]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH qemu v2 5/5] hw/cxl/events: Updates for rev3.2 memory module event record
2026-01-02 15:15 ` [PATCH qemu v2 5/5] hw/cxl/events: Updates for rev3.2 memory module " Jonathan Cameron
@ 2026-01-12 12:20 ` Markus Armbruster
2026-01-12 12:23 ` Markus Armbruster
1 sibling, 0 replies; 16+ messages in thread
From: Markus Armbruster @ 2026-01-12 12:20 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Michael Tsirkin, qemu-devel, shiju.jose, linuxarm, linux-cxl,
Ravi Shankar
Jonathan Cameron <Jonathan.Cameron@huawei.com> writes:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> CXL spec rev3.2 section 8.2.10.2.1.3 Table 8-50, memory module
> event record has updated with following new fields.
> 1. Validity Flags
> 2. Component Identifier
> 3. Device Event Sub-Type
>
> Add updates for the above spec changes in the CXL memory module
> event reporting and QMP command to inject memory module event.
>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> qapi/cxl.json | 12 +++++++++++-
> include/hw/cxl/cxl_events.h | 7 +++++--
> hw/mem/cxl_type3.c | 20 ++++++++++++++++++++
> hw/mem/cxl_type3_stubs.c | 4 ++++
> 4 files changed, 40 insertions(+), 3 deletions(-)
>
> diff --git a/qapi/cxl.json b/qapi/cxl.json
> index 3e4bad4ad0..752d46cda2 100644
> --- a/qapi/cxl.json
> +++ b/qapi/cxl.json
> @@ -242,6 +242,14 @@
##
# @CXLMemModuleEvent:
#
# Event record for a Memory Module Event (CXL r3.0 8.2.9.2.1.3).
#
# @type: Device Event Type. See CXL r3.0 Table 8-45 Memory Module
# Event Record for bit definitions for bit definiions.
#
[...]
> # @corrected-persistent-error-count: Total number of correctable
> # errors in persistent memory
> #
> +# @component-id: Device specific component identifier for the event.
> +# May describe a field replaceable sub-component of the device.
> +#
> +# @is-comp-id-pldm: This flag specifies whether the device-specific
> +# component identifier format follows PLDM.
> +#
> +# @sub-type: Device event sub-type.
> +#
> # Since: 8.1
You're not updating the reference to the CXL spec from 3.0 to 3.2.
Intentional? You do in PATCH 2.
> ##
> { 'struct': 'CXLMemModuleEvent',
> @@ -251,7 +259,9 @@
> 'life-used': 'uint8', 'temperature' : 'int16',
> 'dirty-shutdown-count': 'uint32',
> 'corrected-volatile-error-count': 'uint32',
> - 'corrected-persistent-error-count': 'uint32'
> + 'corrected-persistent-error-count': 'uint32',
> + '*component-id': 'str', '*is-comp-id-pldm':'bool',
> + 'sub-type':'uint8'
> }}
>
> ##
[...]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH qemu v2 5/5] hw/cxl/events: Updates for rev3.2 memory module event record
2026-01-02 15:15 ` [PATCH qemu v2 5/5] hw/cxl/events: Updates for rev3.2 memory module " Jonathan Cameron
2026-01-12 12:20 ` Markus Armbruster
@ 2026-01-12 12:23 ` Markus Armbruster
2026-01-13 17:59 ` Jonathan Cameron
1 sibling, 1 reply; 16+ messages in thread
From: Markus Armbruster @ 2026-01-12 12:23 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Michael Tsirkin, qemu-devel, shiju.jose, linuxarm, linux-cxl,
Ravi Shankar
Jonathan Cameron <Jonathan.Cameron@huawei.com> writes:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> CXL spec rev3.2 section 8.2.10.2.1.3 Table 8-50, memory module
> event record has updated with following new fields.
> 1. Validity Flags
> 2. Component Identifier
> 3. Device Event Sub-Type
>
> Add updates for the above spec changes in the CXL memory module
> event reporting and QMP command to inject memory module event.
>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> qapi/cxl.json | 12 +++++++++++-
> include/hw/cxl/cxl_events.h | 7 +++++--
> hw/mem/cxl_type3.c | 20 ++++++++++++++++++++
> hw/mem/cxl_type3_stubs.c | 4 ++++
> 4 files changed, 40 insertions(+), 3 deletions(-)
>
> diff --git a/qapi/cxl.json b/qapi/cxl.json
> index 3e4bad4ad0..752d46cda2 100644
> --- a/qapi/cxl.json
> +++ b/qapi/cxl.json
> @@ -242,6 +242,14 @@
> # @corrected-persistent-error-count: Total number of correctable
> # errors in persistent memory
> #
> +# @component-id: Device specific component identifier for the event.
> +# May describe a field replaceable sub-component of the device.
> +#
> +# @is-comp-id-pldm: This flag specifies whether the device-specific
> +# component identifier format follows PLDM.
> +#
> +# @sub-type: Device event sub-type.
> +#
These three seem to be the same in CXLGeneralMediaEvent, CXLDRAMEvent,
and CXLMemModuleEvent. Should they live in their common base type
CXLCommonEventBase?
> # Since: 8.1
> ##
> { 'struct': 'CXLMemModuleEvent',
> @@ -251,7 +259,9 @@
> 'life-used': 'uint8', 'temperature' : 'int16',
> 'dirty-shutdown-count': 'uint32',
> 'corrected-volatile-error-count': 'uint32',
> - 'corrected-persistent-error-count': 'uint32'
> + 'corrected-persistent-error-count': 'uint32',
> + '*component-id': 'str', '*is-comp-id-pldm':'bool',
> + 'sub-type':'uint8'
> }}
>
> ##
[...]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH qemu v2 2/5] hw/cxl/events: Update for rev3.2 common event record format
2026-01-12 12:16 ` Markus Armbruster
@ 2026-01-13 17:47 ` Jonathan Cameron
2026-01-14 7:27 ` Markus Armbruster
0 siblings, 1 reply; 16+ messages in thread
From: Jonathan Cameron @ 2026-01-13 17:47 UTC (permalink / raw)
To: Markus Armbruster
Cc: Michael Tsirkin, qemu-devel, shiju.jose, linuxarm, linux-cxl,
Ravi Shankar
On Mon, 12 Jan 2026 13:16:05 +0100
Markus Armbruster <armbru@redhat.com> wrote:
> Jonathan Cameron <Jonathan.Cameron@huawei.com> writes:
>
> > From: Shiju Jose <shiju.jose@huawei.com>
> >
> > CXL spec 3.2 section 8.2.9.2.1 Table 8-55, Common Event Record
> > format has updated with optional Maintenance Operation Subclass,
> > LD ID and ID of the device head information.
> >
> > Add updates for the above optional parameters in the related
> > CXL events reporting and in the QMP commands to inject CXL events.
> >
> > Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Hi Markus,
Thanks for taking a look!
> > ---
> > qapi/cxl.json | 20 ++++++++---
> > include/hw/cxl/cxl_device.h | 7 +++-
> > include/hw/cxl/cxl_events.h | 15 ++++++--
> > hw/cxl/cxl-events.c | 3 +-
> > hw/cxl/cxl-mailbox-utils.c | 3 +-
> > hw/mem/cxl_type3.c | 70 ++++++++++++++++++++++++++++++++-----
> > hw/mem/cxl_type3_stubs.c | 24 +++++++++++--
> > 7 files changed, 121 insertions(+), 21 deletions(-)
> >
> > diff --git a/qapi/cxl.json b/qapi/cxl.json
> > index d5b86159f1..b3c2ac9575 100644
> > --- a/qapi/cxl.json
> > +++ b/qapi/cxl.json
> > @@ -33,20 +33,32 @@
> > ##
> > # @CXLCommonEventBase:
> > #
> > -# Common event base for a CXL Event (CXL r3.0 8.2.9.2.1
> > -# Table 8-42 Common Event Record Format).
> > +# Common event base for a CXL Event (CXL r3.2 8.2.10.2.1
> > +# Table 8-55 Common Event Record Format).
> > #
> > # @path: CXL type 3 device canonical QOM path
> > #
> > # @log: event log to add the event to
> > #
> > -# @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
> > +# @flags: Event Record Flags. See CXL r3.2 Table 8-55 Common Event
> > # Record Format, Event Record Flags for subfield definitions.
> > #
> > +# @maint-op-class: Maintenance operation class the device requests to
> > +# initiate.
> > +#
> > +# @maint-op-subclass: Maintenance operation subclass the device
> > +# requests to initiate.
> > +#
> > +# @ld-id: LD ID of LD from where the event originated.
Logical Device. I'll spell it out the first time. From the glossary:
"LD: Logical Device. Entity that represents a CXL Endpoint that is bound to
a VCS. An SLD contains one LD. An MLD contains multiple LDs."
So what does that actually mean? It's a number that identifies the
bit of a device that is presented to a given host at a particular
point in the PCI topology that we are faking from the underlying CXL
one.
I think best I can do is just spell out the acronyms. If people
want more they need to look at the spec :(
Time for a deeper explanation that probably no one ever wanted :)
From a physical topology point of view think of something like:
vPPDs are virtual downstream ports that assign an LD ID.
HOST 0 HOST 1 Host 3
| | |
RP RP RP
| | |
| | |
__|_________________|______ |
| | SWITCH | | |
| _|_____ _____|_ | |
|| | | | | |
|| | | | | |
|vPPD0 vPPD1 VPPD2 VPPD3 | |
|| | | | | |
||_____________| | | |
| | | | |
|___________DSP0________DSP1| |
| | |
| Some other dev |
Traffic tagged |
with an LD_ID associated with |
a given vPPD (so 2 tags here) |
| |
________________|__________________________|______
| (CXL Device) HEAD0 HEAD1 |
| Now splits up based Only one LD|
| on LD_ID |
|__________________________________________________|
Hosts see:
Used letters for down stream port numbers to avoid
any explicit mapping to the physical ports above.
HOST 0 Host 1 Host3
| | |
RP RP RP
| | |
________|_________ _________|_________ |
| | | | | | |
| ____|____ | | ______|______ | |
| | | | | | | | |
|__DSPA______DSPB__| |__DSPA________DSPB_| |
| | | | |
___|______ Nothing _____|_____ Other dev ___|______
|CXL Type3 | |CXL Type3 | |CXL Type3 |
| (H0, LD0)| | (H0, LD1)| | (H1, LD0)|
|__________| |__________| |__________|
These IDs should only be reported for events that are isolated
(as appropriate) to a head and/or LD and as you can see the hosts
don't actually know these IDs even exist hence there is no need to
report them via in band path. If they don't take the values
that reflect the LD we are actually talking to, then we are
reporting someone else's error! Via out of band / switch CCI we
see the top diagram where we definitely need LD_ID and HEAD_ID
to make any sense of errors, particularly as the memory addresses
in the records are specific to Head/LD pair.
The recommendation of the spec is don't set them for simple reporting
over inband mailboxes. Now you might think we don't have out of band
support upstream yet (my staging CXL tree does have both MCTP over
I2C and USB) but we do have the switch CCI and that can tunnel to
out of band interfaces (technically it's over PCI Vendor defined
messages but in practice it ends up the same from a 'what can I talk
to' point of view as something truely out of band like an I2C bus.
We don't actually have event queues on those yet though... When
we do we'll want this command to queue events there as well as on
for inband path.
So we are adding them now for 2 reasons.
1) The spec allows it even for boring inband event reporting
(recommendation only to not do so) so we need to check the kernel stack
reports correctly.
2) We will want to add event queues on the out of band interfaces and
for those we'll need these IDs.
>
> What's an LD?
>
> > +#
> > +# @head-id: ID of the device head from where the event originated.
>
> Are these identifiers taken from the CXL spec?
Yes. Though feels odd to reference the glossary for the definitions.
>
> > +#
> > # Since: 8.1
> > ##
> > { 'struct': 'CXLCommonEventBase',
> > - 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8' } }
> > + 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint32',
> > + '*maint-op-class':'uint8', '*maint-op-subclass':'uint8',
> > + '*ld-id':'uint16', '*head-id':'uint8' } }
> >
> > ##
> > # @CXLGeneralMediaEvent:
>
> [...]
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH qemu v2 5/5] hw/cxl/events: Updates for rev3.2 memory module event record
2026-01-12 12:23 ` Markus Armbruster
@ 2026-01-13 17:59 ` Jonathan Cameron
2026-01-14 7:29 ` Markus Armbruster
0 siblings, 1 reply; 16+ messages in thread
From: Jonathan Cameron @ 2026-01-13 17:59 UTC (permalink / raw)
To: Markus Armbruster
Cc: Michael Tsirkin, qemu-devel, shiju.jose, linuxarm, linux-cxl,
Ravi Shankar
On Mon, 12 Jan 2026 13:23:27 +0100
Markus Armbruster <armbru@redhat.com> wrote:
> Jonathan Cameron <Jonathan.Cameron@huawei.com> writes:
>
> > From: Shiju Jose <shiju.jose@huawei.com>
> >
> > CXL spec rev3.2 section 8.2.10.2.1.3 Table 8-50, memory module
> > event record has updated with following new fields.
> > 1. Validity Flags
> > 2. Component Identifier
> > 3. Device Event Sub-Type
> >
> > Add updates for the above spec changes in the CXL memory module
> > event reporting and QMP command to inject memory module event.
> >
> > Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > ---
> > qapi/cxl.json | 12 +++++++++++-
> > include/hw/cxl/cxl_events.h | 7 +++++--
> > hw/mem/cxl_type3.c | 20 ++++++++++++++++++++
> > hw/mem/cxl_type3_stubs.c | 4 ++++
> > 4 files changed, 40 insertions(+), 3 deletions(-)
> >
> > diff --git a/qapi/cxl.json b/qapi/cxl.json
> > index 3e4bad4ad0..752d46cda2 100644
> > --- a/qapi/cxl.json
> > +++ b/qapi/cxl.json
> > @@ -242,6 +242,14 @@
> > # @corrected-persistent-error-count: Total number of correctable
> > # errors in persistent memory
> > #
> > +# @component-id: Device specific component identifier for the event.
> > +# May describe a field replaceable sub-component of the device.
> > +#
> > +# @is-comp-id-pldm: This flag specifies whether the device-specific
> > +# component identifier format follows PLDM.
> > +#
> > +# @sub-type: Device event sub-type.
> > +#
>
> These three seem to be the same in CXLGeneralMediaEvent, CXLDRAMEvent,
> and CXLMemModuleEvent. Should they live in their common base type
> CXLCommonEventBase?
We have documented that base as corresponding to the spec defined
Common event record header and these aren't part of that. We could
invent a CXLMemCommonEventBase that contains the stuff that is shared
for memory types of errors but it would probably just confuse anyone
trying to correlate this stuff with the spec.
There are a lot more event records we don't yet support, or are not
directly injected because they are responses to some other action.
(e.g. dynamic capacity add produces an event but also changes a bunch
of device state)
I'm not sure if we will add direct injection of any of those other
events in future. Some are errors such as MLD Port Event Records,
but reporting those inband makes no sense as normal PCIe error
reporting is used for that. They are to expose what happened to
an out of band monitoring interface (see examples in patch 2
discussion).
Thanks for all your other feedback. We'll resolve that for v3.
Jonathan
>
> > # Since: 8.1
> > ##
> > { 'struct': 'CXLMemModuleEvent',
> > @@ -251,7 +259,9 @@
> > 'life-used': 'uint8', 'temperature' : 'int16',
> > 'dirty-shutdown-count': 'uint32',
> > 'corrected-volatile-error-count': 'uint32',
> > - 'corrected-persistent-error-count': 'uint32'
> > + 'corrected-persistent-error-count': 'uint32',
> > + '*component-id': 'str', '*is-comp-id-pldm':'bool',
> > + 'sub-type':'uint8'
> > }}
> >
> > ##
>
> [...]
>
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH qemu v2 2/5] hw/cxl/events: Update for rev3.2 common event record format
2026-01-13 17:47 ` Jonathan Cameron
@ 2026-01-14 7:27 ` Markus Armbruster
0 siblings, 0 replies; 16+ messages in thread
From: Markus Armbruster @ 2026-01-14 7:27 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Michael Tsirkin, qemu-devel, shiju.jose, linuxarm, linux-cxl,
Ravi Shankar
Jonathan Cameron <jonathan.cameron@huawei.com> writes:
> On Mon, 12 Jan 2026 13:16:05 +0100
> Markus Armbruster <armbru@redhat.com> wrote:
>
>> Jonathan Cameron <Jonathan.Cameron@huawei.com> writes:
>>
>> > From: Shiju Jose <shiju.jose@huawei.com>
>> >
>> > CXL spec 3.2 section 8.2.9.2.1 Table 8-55, Common Event Record
>> > format has updated with optional Maintenance Operation Subclass,
>> > LD ID and ID of the device head information.
>> >
>> > Add updates for the above optional parameters in the related
>> > CXL events reporting and in the QMP commands to inject CXL events.
>> >
>> > Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
>> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> Hi Markus,
> Thanks for taking a look!
You're welcome!
>> > ---
>> > qapi/cxl.json | 20 ++++++++---
>> > include/hw/cxl/cxl_device.h | 7 +++-
>> > include/hw/cxl/cxl_events.h | 15 ++++++--
>> > hw/cxl/cxl-events.c | 3 +-
>> > hw/cxl/cxl-mailbox-utils.c | 3 +-
>> > hw/mem/cxl_type3.c | 70 ++++++++++++++++++++++++++++++++-----
>> > hw/mem/cxl_type3_stubs.c | 24 +++++++++++--
>> > 7 files changed, 121 insertions(+), 21 deletions(-)
>> >
>> > diff --git a/qapi/cxl.json b/qapi/cxl.json
>> > index d5b86159f1..b3c2ac9575 100644
>> > --- a/qapi/cxl.json
>> > +++ b/qapi/cxl.json
>> > @@ -33,20 +33,32 @@
>> > ##
>> > # @CXLCommonEventBase:
>> > #
>> > -# Common event base for a CXL Event (CXL r3.0 8.2.9.2.1
>> > -# Table 8-42 Common Event Record Format).
>> > +# Common event base for a CXL Event (CXL r3.2 8.2.10.2.1
>> > +# Table 8-55 Common Event Record Format).
>> > #
>> > # @path: CXL type 3 device canonical QOM path
>> > #
>> > # @log: event log to add the event to
>> > #
>> > -# @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
>> > +# @flags: Event Record Flags. See CXL r3.2 Table 8-55 Common Event
>> > # Record Format, Event Record Flags for subfield definitions.
>> > #
>> > +# @maint-op-class: Maintenance operation class the device requests to
>> > +# initiate.
>> > +#
>> > +# @maint-op-subclass: Maintenance operation subclass the device
>> > +# requests to initiate.
>> > +#
>> > +# @ld-id: LD ID of LD from where the event originated.
>>
>> What's an LD?
>
> Logical Device. I'll spell it out the first time.
Yes, please.
> From the glossary:
> "LD: Logical Device. Entity that represents a CXL Endpoint that is bound to
> a VCS. An SLD contains one LD. An MLD contains multiple LDs."
A line of acronyms marching ponderously across the page... made me laugh
:)
> So what does that actually mean? It's a number that identifies the
> bit of a device that is presented to a given host at a particular
> point in the PCI topology that we are faking from the underlying CXL
> one.
>
> I think best I can do is just spell out the acronyms. If people
> want more they need to look at the spec :(
Fair!
> Time for a deeper explanation that probably no one ever wanted :)
>
> From a physical topology point of view think of something like:
>
> vPPDs are virtual downstream ports that assign an LD ID.
>
> HOST 0 HOST 1 Host 3
> | | |
> RP RP RP
> | | |
> | | |
> __|_________________|______ |
> | | SWITCH | | |
> | _|_____ _____|_ | |
> || | | | | |
> || | | | | |
> |vPPD0 vPPD1 VPPD2 VPPD3 | |
> || | | | | |
> ||_____________| | | |
> | | | | |
> |___________DSP0________DSP1| |
> | | |
> | Some other dev |
> Traffic tagged |
> with an LD_ID associated with |
> a given vPPD (so 2 tags here) |
> | |
> ________________|__________________________|______
> | (CXL Device) HEAD0 HEAD1 |
> | Now splits up based Only one LD|
> | on LD_ID |
> |__________________________________________________|
>
>
> Hosts see:
> Used letters for down stream port numbers to avoid
> any explicit mapping to the physical ports above.
>
>
> HOST 0 Host 1 Host3
> | | |
> RP RP RP
> | | |
> ________|_________ _________|_________ |
> | | | | | | |
> | ____|____ | | ______|______ | |
> | | | | | | | | |
> |__DSPA______DSPB__| |__DSPA________DSPB_| |
> | | | | |
> ___|______ Nothing _____|_____ Other dev ___|______
> |CXL Type3 | |CXL Type3 | |CXL Type3 |
> | (H0, LD0)| | (H0, LD1)| | (H1, LD0)|
> |__________| |__________| |__________|
>
> These IDs should only be reported for events that are isolated
> (as appropriate) to a head and/or LD and as you can see the hosts
> don't actually know these IDs even exist hence there is no need to
> report them via in band path. If they don't take the values
> that reflect the LD we are actually talking to, then we are
> reporting someone else's error! Via out of band / switch CCI we
> see the top diagram where we definitely need LD_ID and HEAD_ID
> to make any sense of errors, particularly as the memory addresses
> in the records are specific to Head/LD pair.
>
> The recommendation of the spec is don't set them for simple reporting
> over inband mailboxes. Now you might think we don't have out of band
> support upstream yet (my staging CXL tree does have both MCTP over
> I2C and USB) but we do have the switch CCI and that can tunnel to
> out of band interfaces (technically it's over PCI Vendor defined
> messages but in practice it ends up the same from a 'what can I talk
> to' point of view as something truely out of band like an I2C bus.
> We don't actually have event queues on those yet though... When
> we do we'll want this command to queue events there as well as on
> for inband path.
Truly more than I ever wanted ;)
> So we are adding them now for 2 reasons.
> 1) The spec allows it even for boring inband event reporting
> (recommendation only to not do so) so we need to check the kernel stack
> reports correctly.
> 2) We will want to add event queues on the out of band interfaces and
> for those we'll need these IDs.
Makes sense. Thanks!
>> > +#
>> > +# @head-id: ID of the device head from where the event originated.
>>
>> Are these identifiers taken from the CXL spec?
> Yes. Though feels odd to reference the glossary for the definitions.
Since they are from the CXL spec, I don't need to think about names that
are more in line with established QAPI naming conventions. That's why I
asked. We're good there.
>> > +#
>> > # Since: 8.1
>> > ##
>> > { 'struct': 'CXLCommonEventBase',
>> > - 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8' } }
>> > + 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint32',
>> > + '*maint-op-class':'uint8', '*maint-op-subclass':'uint8',
>> > + '*ld-id':'uint16', '*head-id':'uint8' } }
>> >
>> > ##
>> > # @CXLGeneralMediaEvent:
>>
>> [...]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH qemu v2 5/5] hw/cxl/events: Updates for rev3.2 memory module event record
2026-01-13 17:59 ` Jonathan Cameron
@ 2026-01-14 7:29 ` Markus Armbruster
0 siblings, 0 replies; 16+ messages in thread
From: Markus Armbruster @ 2026-01-14 7:29 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Michael Tsirkin, qemu-devel, shiju.jose, linuxarm, linux-cxl,
Ravi Shankar
Jonathan Cameron <jonathan.cameron@huawei.com> writes:
> On Mon, 12 Jan 2026 13:23:27 +0100
> Markus Armbruster <armbru@redhat.com> wrote:
>
>> Jonathan Cameron <Jonathan.Cameron@huawei.com> writes:
>>
>> > From: Shiju Jose <shiju.jose@huawei.com>
>> >
>> > CXL spec rev3.2 section 8.2.10.2.1.3 Table 8-50, memory module
>> > event record has updated with following new fields.
>> > 1. Validity Flags
>> > 2. Component Identifier
>> > 3. Device Event Sub-Type
>> >
>> > Add updates for the above spec changes in the CXL memory module
>> > event reporting and QMP command to inject memory module event.
>> >
>> > Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
>> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> > ---
>> > qapi/cxl.json | 12 +++++++++++-
>> > include/hw/cxl/cxl_events.h | 7 +++++--
>> > hw/mem/cxl_type3.c | 20 ++++++++++++++++++++
>> > hw/mem/cxl_type3_stubs.c | 4 ++++
>> > 4 files changed, 40 insertions(+), 3 deletions(-)
>> >
>> > diff --git a/qapi/cxl.json b/qapi/cxl.json
>> > index 3e4bad4ad0..752d46cda2 100644
>> > --- a/qapi/cxl.json
>> > +++ b/qapi/cxl.json
>> > @@ -242,6 +242,14 @@
>> > # @corrected-persistent-error-count: Total number of correctable
>> > # errors in persistent memory
>> > #
>> > +# @component-id: Device specific component identifier for the event.
>> > +# May describe a field replaceable sub-component of the device.
>> > +#
>> > +# @is-comp-id-pldm: This flag specifies whether the device-specific
>> > +# component identifier format follows PLDM.
>> > +#
>> > +# @sub-type: Device event sub-type.
>> > +#
>>
>> These three seem to be the same in CXLGeneralMediaEvent, CXLDRAMEvent,
>> and CXLMemModuleEvent. Should they live in their common base type
>> CXLCommonEventBase?
>
> We have documented that base as corresponding to the spec defined
> Common event record header and these aren't part of that. We could
> invent a CXLMemCommonEventBase that contains the stuff that is shared
> for memory types of errors but it would probably just confuse anyone
> trying to correlate this stuff with the spec.
>
> There are a lot more event records we don't yet support, or are not
> directly injected because they are responses to some other action.
> (e.g. dynamic capacity add produces an event but also changes a bunch
> of device state)
>
> I'm not sure if we will add direct injection of any of those other
> events in future. Some are errors such as MLD Port Event Records,
> but reporting those inband makes no sense as normal PCIe error
> reporting is used for that. They are to expose what happened to
> an out of band monitoring interface (see examples in patch 2
> discussion).
I gladly defer to your expert opinion here. We can always factor out
later.
> Thanks for all your other feedback. We'll resolve that for v3.
>
> Jonathan
[...]
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2026-01-14 7:29 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-01-02 15:15 [PATCH qemu v2 0/5] cxl: r3.2 specification event updates Jonathan Cameron
2026-01-02 15:15 ` [PATCH qemu v2 1/5] qapi: cxl: Refactor CXL event injection for common commands arguments Jonathan Cameron
2026-01-12 12:12 ` Markus Armbruster
2026-01-02 15:15 ` [PATCH qemu v2 2/5] hw/cxl/events: Update for rev3.2 common event record format Jonathan Cameron
2026-01-12 12:16 ` Markus Armbruster
2026-01-13 17:47 ` Jonathan Cameron
2026-01-14 7:27 ` Markus Armbruster
2026-01-02 15:15 ` [PATCH qemu v2 3/5] hw/cxl/events: Updates for rev3.2 general media event record Jonathan Cameron
2026-01-12 12:18 ` Markus Armbruster
2026-01-02 15:15 ` [PATCH qemu v2 4/5] hw/cxl/events: Updates for rev3.2 DRAM " Jonathan Cameron
2026-01-12 12:19 ` Markus Armbruster
2026-01-02 15:15 ` [PATCH qemu v2 5/5] hw/cxl/events: Updates for rev3.2 memory module " Jonathan Cameron
2026-01-12 12:20 ` Markus Armbruster
2026-01-12 12:23 ` Markus Armbruster
2026-01-13 17:59 ` Jonathan Cameron
2026-01-14 7:29 ` Markus Armbruster
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