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From: sashiko-bot@kernel.org
To: alejandro.lucero-palau@amd.com
Cc: linux-cxl@vger.kernel.org
Subject: Re: [PATCH v31 2/5] sfc: Map cxl regs
Date: Tue, 30 Jun 2026 14:39:20 +0000	[thread overview]
Message-ID: <20260630143920.BCF7C1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260630151346.31201-3-alejandro.lucero-palau@amd.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The commit adds `#include <cxl/pci.h>`, but `include/cxl/pci.h` does not exist in the kernel tree, resulting in a fatal compilation error.
--

commit fd1792aaa5cf6782d5137f23ed3db63b260303d5
Author: Alejandro Lucero <alucerop@amd.com>

sfc: Map cxl regs

This commit introduces CXL core functions to the SFC driver for discovering
and mapping CXL device registers. It sets up the component registers and
verifies the presence of HDM and RAS capabilities.

> diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c
> index be252af972ab3..704b0ebae9374 100644
> --- a/drivers/net/ethernet/sfc/efx_cxl.c
> +++ b/drivers/net/ethernet/sfc/efx_cxl.c
> @@ -7,6 +7,8 @@
>  
>  #include <linux/pci.h>
>  
> +#include <cxl/cxl.h>
> +#include <cxl/pci.h>

[Severity: Low]
Is this the correct header path? The cxl/pci.h file doesn't appear to exist
in the kernel tree. The cxl_pci_setup_regs() function and the
CXL_REGLOC_RBI_COMPONENT enum seem to be defined in drivers/cxl/cxlpci.h,
which is internal to the CXL subsystem and not exposed to other drivers.
Will this cause a build failure when compiling the sfc driver?

[ ... ]

> @@ -42,6 +45,29 @@ int efx_cxl_init(struct efx_probe_data *probe_data)
>  	if (!cxl)
>  		return -ENOMEM;
>  
> +	rc = cxl_pci_setup_regs(pci_dev, CXL_REGLOC_RBI_COMPONENT,
> +				&cxl->cxlds.reg_map);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260630151346.31201-1-alejandro.lucero-palau@amd.com?part=2

  reply	other threads:[~2026-06-30 14:39 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-30 15:13 [PATCH v31 0/5] Type2 device basic support alejandro.lucero-palau
2026-06-30 15:13 ` [PATCH v31 1/5] sfc: add cxl support alejandro.lucero-palau
2026-06-30 15:13 ` [PATCH v31 2/5] sfc: Map cxl regs alejandro.lucero-palau
2026-06-30 14:39   ` sashiko-bot [this message]
2026-06-30 15:13 ` [PATCH v31 3/5] sfc: Initialize cxl dpa alejandro.lucero-palau
2026-06-30 14:52   ` sashiko-bot
2026-06-30 15:13 ` [PATCH v31 4/5] sfc: obtain and map cxl range using devm_cxl_probe_mem alejandro.lucero-palau
2026-06-30 15:04   ` sashiko-bot
2026-06-30 15:13 ` [PATCH v31 5/5] sfc: support pio mapping based on cxl alejandro.lucero-palau
2026-06-30 15:22   ` sashiko-bot

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