Re: [PATCH v31 5/5] sfc: support pio mapping based on cxl

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Critical] Missing VI base and PIO register offsets in CXL PIO mapping, leading to hardware register corruption
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commit 125e7b168b7494938907570e29acc3c906cb9a0a
Author: Alejandro Lucero <alucerop@amd.com>

sfc: support pio mapping based on cxl

This patch adds support for mapping PIO buffers using CXL memory if the device
supports it and is successfully initialized. Using CXL for the PIO buffer region
can help further reduce latency during TX packet exchanges.

> diff --git a/drivers/net/ethernet/sfc/ef10.c b/drivers/net/ethernet/sfc/ef10.c
> index 7e04f115bbaaa..73bc064929f63 100644
> --- a/drivers/net/ethernet/sfc/ef10.c
> +++ b/drivers/net/ethernet/sfc/ef10.c
[ ... ]
> @@ -1263,8 +1273,23 @@ static int efx_ef10_dimension_resources(struct efx_nic *efx)
>  	iounmap(efx->membase);
>  	efx->membase = membase;
>  
> -	/* Set up the WC mapping if needed */
> -	if (wc_mem_map_size) {
> +	if (!wc_mem_map_size)
> +		goto skip_pio;
> +
> +	/* Set up the WC mapping */
> +
> +#ifdef CONFIG_SFC_CXL
> +	probe_data = container_of(efx, struct efx_probe_data, efx);
> +	if ((nic_data->datapath_caps3 &
> +	    (1 << MC_CMD_GET_CAPABILITIES_V7_OUT_CXL_CONFIG_ENABLE_LBN)) &&
> +	    probe_data->cxl_pio_initialised) {
> +		/* Using PIO through CXL mapping */
> +		nic_data->pio_write_base = probe_data->cxl->ctpio_cxl;

[Severity: Critical]
Does this assignment miss the required hardware offsets for the VI base and PIO
buffer register?

In the legacy PIO BAR mapping path just below, the base is calculated with
these offsets:

    pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF - uc_mem_map_size

When efx_ef10_link_piobufs() sets up the TX queue, it computes the pointer
using this base:

    tx_queue->piobuf =
        nic_data->pio_write_base +
        index * efx->vi_stride + offset;

Without adding the VI base and PIO register offsets to the CXL mapping,
will the calculated pointer target the doorbell registers at offset 0
(e.g., ER_DZ_EVQ_RPTR, ER_DZ_TX_DESC_UPD) instead of the PIO buffers,
causing packet data writes to corrupt hardware state?

> +		nic_data->pio_write_vi_base = pio_write_vi_base;
> +	} else
> +#endif
> +	{
> +		/* Using legacy PIO BAR mapping */
>  		nic_data->wc_membase = ioremap_wc(efx->membase_phys +
>  						  uc_mem_map_size,
>  						  wc_mem_map_size);

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Sashiko AI review · https://sashiko.dev/#/patchset/20260630151346.31201-1-alejandro.lucero-palau@amd.com?part=5