From: sashiko-bot@kernel.org
To: "Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>
Cc: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v2 09/13] PCI/CXL: Disable and re-enable CXL regions
Date: Tue, 25 Aug 2026 02:39:36 +0000 [thread overview]
Message-ID: <20260825023936.A65AF1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260825022628.3651434-10-fabio.m.de.francesco@linux.intel.com>
Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] `cxl_sbr_enable_regions()` silently ignores the return value of `cxl_sbr_collect_regions()`, leading to permanently disabled regions on allocation failure.
- [High] The global `cxl_sbr_region_ops` pointer can dangle if `cxl_driver_register()` fails, and lacks module pinning to protect against concurrent unloads.
- [High] `cxl_sbr_enable_regions()` unconditionally re-enables regions even if HDM decoder restoration fails.
- [Medium] The recommit path incorrectly treats legitimately missing HDM state (e.g., ports without devices, or emulated decoders) as a failure or logs spurious warnings.
--
--- Patch [9]: [PATCH v2 09/13] PCI/CXL: Disable and re-enable CXL regions ---
commit cfc12109c423de14f05ed1c759bffe4684c3373e
Author: Fabio M. De Francesco <fabio.m.de.francesco@linux.intel.com>
PCI/CXL: Disable and re-enable CXL regions
A Secondary Bus Reset of a CXL Downstream Port needs every CXL region
routed through that Port disabled for the duration. This patch adds
callbacks to collect and disable those regions before the reset, and
subsequently restore HDM decoders and re-enable the regions afterward.
> diff --git a/drivers/cxl/core/dport_sbr.c b/drivers/cxl/core/dport_sbr.c
> index 233499bc1fad9..2b6f840e22a7d 100644
> --- a/drivers/cxl/core/dport_sbr.c
> +++ b/drivers/cxl/core/dport_sbr.c
[ ... ]
> +static void cxl_sbr_enable_regions(struct pci_dev *dport_pci)
> +{
> + struct xarray *hdm_state;
> + struct cxl_region *cxlr;
> + struct xarray regions;
> + unsigned long index;
> +
> + xa_init(®ions);
> +
> + cxl_sbr_collect_regions(dport_pci, ®ions);
[Severity: High]
Does this code need to check the return value of cxl_sbr_collect_regions()?
If xa_insert() fails inside cxl_sbr_collect_regions():
rc = xa_insert(regions, (unsigned long)cxlr, cxlr, GFP_KERNEL);
if (rc) {
put_device(&cxlr->dev);
return rc;
}
it returns an error and stops collecting. By discarding the return value here,
could this silently skip some regions and leave them permanently offline and
unbound?
> +
> + hdm_state = xa_load(&cxl_sbr_hdm_state, (unsigned long)dport_pci);
> + if (hdm_state)
> + cxl_sbr_recommit_decoders(dport_pci, hdm_state);
> + else
> + pci_warn(dport_pci, "no saved HDM state, decode not restored\n");
[Severity: Medium]
Is it possible for ports to legitimately have no HDM state (like ports without
devices or with emulated decoders)?
The save path in cxl_port_save_hdm_state() appears to correctly skip such
ports without saving state. If that happens, wouldn't this path log a spurious
warning? Furthermore, wouldn't the recommit path in
cxl_port_recommit_decoders() incorrectly treat missing states as an -ENODATA
failure?
[Severity: High]
Since cxl_sbr_recommit_decoders() returns void, how does this code handle a
hardware programming failure?
If cxl_sbr_recommit_decoders() fails to reprogram the HDM decoders (e.g., due
to device timeout), won't the subsequent loop unconditionally call
cxl_region_enable() and rebind the region driver while the hardware is still
misconfigured? Could this lead to invalid memory accesses?
> +
> + xa_for_each(®ions, index, cxlr)
> + cxl_region_enable(cxlr);
> +
> + cxl_sbr_put_regions(®ions);
> + cxl_sbr_drop_hdm_state(dport_pci);
> +}
[ ... ]
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index fc0bec991a693..d1dd4924fba17 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
[ ... ]
> @@ -4263,12 +4264,14 @@ static struct cxl_driver cxl_region_driver = {
>
> int cxl_region_init(void)
> {
> + pci_cxl_set_sbr_region_ops(&cxl_sbr_region_ops);
> return cxl_driver_register(&cxl_region_driver);
> }
[Severity: High]
If cxl_driver_register() fails here, does the PCI subsystem retain a dangling
pointer to cxl_sbr_region_ops?
Also, since the PCI core doesn't hold a module reference, is there a risk of
the module being concurrently unloaded while a Secondary Bus Reset is in
progress?
>
> void cxl_region_exit(void)
> {
> cxl_driver_unregister(&cxl_region_driver);
> + pci_cxl_set_sbr_region_ops(NULL);
> }
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260825022628.3651434-1-fabio.m.de.francesco@linux.intel.com?part=9
next prev parent reply other threads:[~2026-08-25 2:39 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-25 2:26 [PATCH v2 00/13] Make SBR work for CXL Downstream Ports Fabio M. De Francesco
2026-08-25 2:26 ` [PATCH v2 01/13] cxl/pci: Make the HDM and Mem_Enable writes callable from CXL Fabio M. De Francesco
2026-08-25 2:37 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 02/13] cxl/hdm: Add function to restore one HDM decoder Fabio M. De Francesco
2026-08-25 2:41 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 03/13] cxl/hdm: Add function to restore CXL.mem decode Fabio M. De Francesco
2026-08-25 2:45 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 04/13] cxl/hdm: Reprogram the HDM Decoders below a CXL Port Fabio M. De Francesco
2026-08-25 2:58 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 05/13] cxl/core: Restore the HDM decoders below DPort Fabio M. De Francesco
2026-08-25 2:43 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 06/13] drivers/base/memory: Add cxl_offline_memory() to offline a physical range Fabio M. De Francesco
2026-08-25 2:40 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 07/13] cxl/core: Add region disable and enable for a DPort SBR Fabio M. De Francesco
2026-08-25 2:44 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 08/13] cxl/core: Collect the regions routed through a DPort Fabio M. De Francesco
2026-08-25 2:41 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 09/13] PCI/CXL: Disable and re-enable CXL regions Fabio M. De Francesco
2026-08-25 2:39 ` sashiko-bot [this message]
2026-08-26 9:04 ` Richard Cheng
2026-08-25 2:26 ` [PATCH v2 10/13] PCI/CXL: Clear ACS SV across an SBR of a CXL DPort Fabio M. De Francesco
2026-08-25 2:40 ` sashiko-bot
2026-08-26 8:47 ` Richard Cheng
2026-08-25 2:26 ` [PATCH v2 11/13] PCI/DPC: Unbind regions for DPC recovery Fabio M. De Francesco
2026-08-25 2:51 ` sashiko-bot
2026-08-26 8:54 ` Richard Cheng
2026-08-25 2:26 ` [PATCH v2 12/13] PCI/CXL: Add a sysfs entry to unmask SBR Fabio M. De Francesco
2026-08-25 2:51 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 13/13] PCI/CXL: Refuse an SBR of a CXL DPort unless authorized Fabio M. De Francesco
2026-08-25 2:59 ` sashiko-bot
2026-08-26 9:21 ` [PATCH v2 00/13] Make SBR work for CXL Downstream Ports Richard Cheng
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