From: sashiko-bot@kernel.org
To: "Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>
Cc: linux-pci@vger.kernel.org, linux-cxl@vger.kernel.org
Subject: Re: [PATCH v2 03/13] cxl/hdm: Add function to restore CXL.mem decode
Date: Tue, 25 Aug 2026 02:45:46 +0000 [thread overview]
Message-ID: <20260825024547.3867A1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260825022628.3651434-4-fabio.m.de.francesco@linux.intel.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] `cxl_trigger_poison_list()` can trigger a kernel panic by dereferencing an ERR_PTR when checking `is_cxl_endpoint(port)`.
--
--- Patch [3]: [PATCH v2 03/13] cxl/hdm: Add function to restore CXL.mem decode ---
commit 3dc5dc9495c42e77bea8b303acf10562a2ca0f7a
Author: Fabio M. De Francesco <fabio.m.de.francesco@linux.intel.com>
cxl/hdm: Add function to restore CXL.mem decode
This commit adds a function to put an endpoint back in HDM decode before
its decoders are committed again. It takes the Global Control value to
enable decode and skips endpoints that decode through DVSEC ranges.
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index d55d764895f88..7c898c60f60f6 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
[ ... ]
> +int cxl_endpoint_enable_hdm_decode(struct cxl_memdev *cxlmd, u32 global_ctrl)
> +{
> + struct cxl_port *endpoint = cxlmd->endpoint;
[Severity: High]
This is a pre-existing issue, but since we are accessing cxlmd->endpoint
here, can this endpoint be an error pointer that causes a panic elsewhere?
Looking at cxl_trigger_poison_list() in drivers/cxl/core/memdev.c, if a
privileged user writes to the sysfs attribute trigger_poison_list early:
port = cxlmd->endpoint;
if (!port || !is_cxl_endpoint(port))
return -EINVAL;
If the sysfs attribute is accessed before bus enumeration completes, or if
enumeration fails on a device lacking DVSEC capabilities, cxlmd->endpoint
remains set to ERR_PTR(-ENXIO).
The !port check evaluates to false for an ERR_PTR, and the error pointer is
then passed to is_cxl_endpoint(), which blindly dereferences it causing an
invalid memory access and a kernel panic.
Could this be prevented by using IS_ERR_OR_NULL() instead when validating
the port?
> + struct cxl_hdm *cxlhdm = dev_get_drvdata(&endpoint->dev);
> + int rc;
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260825022628.3651434-1-fabio.m.de.francesco@linux.intel.com?part=3
next prev parent reply other threads:[~2026-08-25 2:45 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-25 2:26 [PATCH v2 00/13] Make SBR work for CXL Downstream Ports Fabio M. De Francesco
2026-08-25 2:26 ` [PATCH v2 01/13] cxl/pci: Make the HDM and Mem_Enable writes callable from CXL Fabio M. De Francesco
2026-08-25 2:37 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 02/13] cxl/hdm: Add function to restore one HDM decoder Fabio M. De Francesco
2026-08-25 2:41 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 03/13] cxl/hdm: Add function to restore CXL.mem decode Fabio M. De Francesco
2026-08-25 2:45 ` sashiko-bot [this message]
2026-08-25 2:26 ` [PATCH v2 04/13] cxl/hdm: Reprogram the HDM Decoders below a CXL Port Fabio M. De Francesco
2026-08-25 2:58 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 05/13] cxl/core: Restore the HDM decoders below DPort Fabio M. De Francesco
2026-08-25 2:43 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 06/13] drivers/base/memory: Add cxl_offline_memory() to offline a physical range Fabio M. De Francesco
2026-08-25 2:40 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 07/13] cxl/core: Add region disable and enable for a DPort SBR Fabio M. De Francesco
2026-08-25 2:44 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 08/13] cxl/core: Collect the regions routed through a DPort Fabio M. De Francesco
2026-08-25 2:41 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 09/13] PCI/CXL: Disable and re-enable CXL regions Fabio M. De Francesco
2026-08-25 2:39 ` sashiko-bot
2026-08-26 9:04 ` Richard Cheng
2026-08-25 2:26 ` [PATCH v2 10/13] PCI/CXL: Clear ACS SV across an SBR of a CXL DPort Fabio M. De Francesco
2026-08-25 2:40 ` sashiko-bot
2026-08-26 8:47 ` Richard Cheng
2026-08-25 2:26 ` [PATCH v2 11/13] PCI/DPC: Unbind regions for DPC recovery Fabio M. De Francesco
2026-08-25 2:51 ` sashiko-bot
2026-08-26 8:54 ` Richard Cheng
2026-08-25 2:26 ` [PATCH v2 12/13] PCI/CXL: Add a sysfs entry to unmask SBR Fabio M. De Francesco
2026-08-25 2:51 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 13/13] PCI/CXL: Refuse an SBR of a CXL DPort unless authorized Fabio M. De Francesco
2026-08-25 2:59 ` sashiko-bot
2026-08-26 9:21 ` [PATCH v2 00/13] Make SBR work for CXL Downstream Ports Richard Cheng
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