From: sashiko-bot@kernel.org
To: "Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>
Cc: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v2 12/13] PCI/CXL: Add a sysfs entry to unmask SBR
Date: Tue, 25 Aug 2026 02:51:23 +0000 [thread overview]
Message-ID: <20260825025123.CB7231F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260825022628.3651434-13-fabio.m.de.francesco@linux.intel.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Concurrent writes to the `cxl_unmask_sbr` bitfield via the sysfs store function can corrupt adjacent bitfields in `struct pci_dev` due to non-atomic read-modify-write operations.
--
--- Patch [12]: [PATCH v2 12/13] PCI/CXL: Add a sysfs entry to unmask SBR ---
commit d915ae90bb0b4f81c466e6e9be4cc5b40f737fbb
Author: Fabio M. De Francesco <fabio.m.de.francesco@linux.intel.com>
PCI/CXL: Add a sysfs entry to unmask SBR
A Secondary Bus Reset of a CXL Downstream Port only reaches the component
below it when the Port's Unmask SBR bit is set. This commit adds a
cxl_unmask_sbr sysfs attribute to allow the kernel to trigger an SBR of
CXL DPorts.
> diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
> --- a/drivers/pci/pci-sysfs.c
> +++ b/drivers/pci/pci-sysfs.c
[ ... ]
> @@ -573,6 +573,33 @@ static ssize_t reset_subordinate_store(struct device *dev,
> }
> static DEVICE_ATTR_WO(reset_subordinate);
>
> +static ssize_t cxl_unmask_sbr_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct pci_dev *pdev = to_pci_dev(dev);
> +
> + return sysfs_emit(buf, "%u\n", pdev->cxl_unmask_sbr);
> +}
> +
> +static ssize_t cxl_unmask_sbr_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t count)
> +{
> + struct pci_dev *pdev = to_pci_dev(dev);
> + unsigned long val;
> +
> + if (!capable(CAP_SYS_ADMIN))
> + return -EPERM;
> +
> + if (kstrtoul(buf, 0, &val) < 0)
> + return -EINVAL;
> +
> + pdev->cxl_unmask_sbr = !!val;
[Severity: High]
Does writing to this bitfield without synchronization risk corrupting adjacent
state flags in struct pci_dev?
Modifying a C bitfield is a non-atomic read-modify-write operation on the
containing 32-bit word.
If a user writes to this sysfs file while the kernel concurrently modifies
other flags sharing this word (like is_busmaster, msi_enabled, or
state_saved), could this silently overwrite those updates?
> +
> + return count;
> +}
> +static DEVICE_ATTR_RW(cxl_unmask_sbr);
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
[ ... ]
> @@ -485,6 +485,7 @@ struct pci_dev {
> unsigned int shpc_managed:1; /* SHPC owned by shpchp */
> unsigned int is_thunderbolt:1; /* Thunderbolt controller */
> unsigned int is_cxl:1; /* Compute Express Link (CXL) */
> + unsigned int cxl_unmask_sbr:1; /* SBR unmask allowed by user */
> /*
> * Devices marked being untrusted are the ones that can potentially
> * execute DMA attacks and similar. They are typically connected
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260825022628.3651434-1-fabio.m.de.francesco@linux.intel.com?part=12
next prev parent reply other threads:[~2026-08-25 2:51 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-25 2:26 [PATCH v2 00/13] Make SBR work for CXL Downstream Ports Fabio M. De Francesco
2026-08-25 2:26 ` [PATCH v2 01/13] cxl/pci: Make the HDM and Mem_Enable writes callable from CXL Fabio M. De Francesco
2026-08-25 2:37 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 02/13] cxl/hdm: Add function to restore one HDM decoder Fabio M. De Francesco
2026-08-25 2:41 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 03/13] cxl/hdm: Add function to restore CXL.mem decode Fabio M. De Francesco
2026-08-25 2:45 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 04/13] cxl/hdm: Reprogram the HDM Decoders below a CXL Port Fabio M. De Francesco
2026-08-25 2:58 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 05/13] cxl/core: Restore the HDM decoders below DPort Fabio M. De Francesco
2026-08-25 2:43 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 06/13] drivers/base/memory: Add cxl_offline_memory() to offline a physical range Fabio M. De Francesco
2026-08-25 2:40 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 07/13] cxl/core: Add region disable and enable for a DPort SBR Fabio M. De Francesco
2026-08-25 2:44 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 08/13] cxl/core: Collect the regions routed through a DPort Fabio M. De Francesco
2026-08-25 2:41 ` sashiko-bot
2026-08-25 2:26 ` [PATCH v2 09/13] PCI/CXL: Disable and re-enable CXL regions Fabio M. De Francesco
2026-08-25 2:39 ` sashiko-bot
2026-08-26 9:04 ` Richard Cheng
2026-08-25 2:26 ` [PATCH v2 10/13] PCI/CXL: Clear ACS SV across an SBR of a CXL DPort Fabio M. De Francesco
2026-08-25 2:40 ` sashiko-bot
2026-08-26 8:47 ` Richard Cheng
2026-08-25 2:26 ` [PATCH v2 11/13] PCI/DPC: Unbind regions for DPC recovery Fabio M. De Francesco
2026-08-25 2:51 ` sashiko-bot
2026-08-26 8:54 ` Richard Cheng
2026-08-25 2:26 ` [PATCH v2 12/13] PCI/CXL: Add a sysfs entry to unmask SBR Fabio M. De Francesco
2026-08-25 2:51 ` sashiko-bot [this message]
2026-08-25 2:26 ` [PATCH v2 13/13] PCI/CXL: Refuse an SBR of a CXL DPort unless authorized Fabio M. De Francesco
2026-08-25 2:59 ` sashiko-bot
2026-08-26 9:21 ` [PATCH v2 00/13] Make SBR work for CXL Downstream Ports Richard Cheng
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