Re: [PATCH v4 3/6] hw/riscv/virt: Advertise the CXL host bridge to firmware via extra-pci-roots

[Junjie Cao <junjie.cao@intel.com>]

Hi Chen Pei,

On Fri, 28 Aug 2026 23:13:02 +0800, Chen Pei wrote:
> +        pci_bus_add_fw_cfg_extra_pci_roots(s->fw_cfg, s->pci_bus,
> +                                           &error_abort);
>      }

On the in-tree edk2 the qtest topology gets PC0C 0x40400000-0x405FFFFF
and bus [0x0C,0x0D] out of build_crs(), and two pxb-cxl (bus_nr 12 and
200) get 0x40000000 and 0x40200000 for their root ports' windows, so
the v3 TODO goes with it and the riscv side is down to this one call.
Your RVA22 run covers the guest side, the memory actually coming
online.

Reviewed-by: Junjie Cao <junjie.cao@intel.com>
Tested-by: Junjie Cao <junjie.cao@intel.com>

One optional thing about placement: select PXB in 1/6 also brings
plain pxb-pcie to riscv virt, and that one needs the same fw_cfg file
with cxl=off -- as posted, a pxb-pcie with cxl=off is never populated
by the firmware. arm/virt, pc and hppa make the call unconditionally,
and the generator returns nothing without an expander root bus, so it
can sit outside the cxl block. Moved here: the pxb-pcie case
enumerates with cxl=off and the four riscv64 ACPI cases still pass.
Here or as a follow-up, your call.

Many thanks,
Junjie