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From: Davidlohr Bueso <dave@stgolabs.net>
To: Li Ming <ming.li@zohomail.com>
Cc: jic23@kernel.org, alison.schofield@intel.com, icheng@nvidia.com,
	benjamin.cheatham@amd.com, alucerop@amd.com,
	dongjoo.seo1@samsung.com, linux-cxl@vger.kernel.org,
	dave.jiang@intel.com
Subject: Re: [PATCH v7 2/8] cxl/pci: Add BI topology enable/disable
Date: Wed, 2 Sep 2026 18:16:36 -0700	[thread overview]
Message-ID: <20260903011636.zflv2y7tmdfc6f3h@offworld> (raw)
In-Reply-To: <a417b52b-41a7-4f90-9231-6abf82ee22a6@zohomail.com>

On Wed, 05 Aug 2026, Li Ming wrote:

>On 7/28/2026 10:41 PM, Davidlohr Bueso wrote:
>> +/* Enable or dealloc BI-ID changes in the given level of the topology. */
>> +static int __cxl_bi_ctrl_dport(struct cxl_dport *dport, bool enable)
>> +{
>> +	struct pci_dev *pdev = to_pci_dev(dport->dport_dev);
>> +	void __iomem *bi = dport->regs.bi_decoder;
>> +	struct cxl_port *port = dport->port;
>> +	u32 ctrl, value;
>> +	int rc;
>> +
>> +	guard(mutex)(&port->bi_lock);
>> +	if (!bi)
>> +		return -EINVAL;
>> +
>> +	ctrl = readl(bi + CXL_BI_DECODER_CTRL_OFFSET);
>> +
>> +	switch (pci_pcie_type(pdev)) {
>> +	case PCI_EXP_TYPE_ROOT_PORT:
>> +		if (enable) {
>> +			/*
>> +			 * There is no point of failure from here on,
>> +			 * BI will be enabled on the endpoint device.
>> +			 */
>> +			dport->nr_bi++;
>> +
>> +			if (FIELD_GET(CXL_BI_DECODER_CTRL_BI_FW, ctrl) &&
>> +			    !FIELD_GET(CXL_BI_DECODER_CTRL_BI_ENABLE, ctrl))
>> +				return 0;
>> +
>> +			value = ctrl | CXL_BI_DECODER_CTRL_BI_FW;
>> +			value &= ~CXL_BI_DECODER_CTRL_BI_ENABLE;
>> +		} else {
>> +			if (WARN_ON_ONCE(dport->nr_bi == 0))
>> +				return -EINVAL;
>> +			if (--dport->nr_bi > 0)
>> +				return 0;
>> +
>> +			value = ctrl & ~(CXL_BI_DECODER_CTRL_BI_FW |
>> +					 CXL_BI_DECODER_CTRL_BI_ENABLE);
>> +		}
>> +
>> +		writel(value, bi + CXL_BI_DECODER_CTRL_OFFSET);
>> +		return 0;
>> +	case PCI_EXP_TYPE_DOWNSTREAM:
>> +		if (enable) {
>> +			value = ctrl & ~CXL_BI_DECODER_CTRL_BI_FW;
>> +			value |= CXL_BI_DECODER_CTRL_BI_ENABLE;
>> +		} else {
>> +			if (!FIELD_GET(CXL_BI_DECODER_CTRL_BI_ENABLE, ctrl))
>> +				return 0;
>> +			value = ctrl & ~(CXL_BI_DECODER_CTRL_BI_FW |
>> +					 CXL_BI_DECODER_CTRL_BI_ENABLE);
>> +		}
>> +
>> +		writel(value, bi + CXL_BI_DECODER_CTRL_OFFSET);
>> +
>> +		rc = __cxl_bi_commit_decoder(dport->dport_dev, bi);
>> +		if (rc)
>> +			return rc;
>> +
>> +		if (port->regs.bi_rt)
>> +			return __cxl_bi_commit_rt(&port->dev, port->regs.bi_rt);
>> +		return 0;
>
>I think another issue here is:
>
>Per CXL r4.0 8.2.4.27.2 Table 8-157. the description of BI  Enable and BI Forward fields.
>
>My understanding is that if a DSP or RP connects to a BI-Capable device directly, the BI Enable field should be set.
>
>Which means if a BI-Capable device is connected to a root port directly, the BI Enable filed of the root port should be set.
>
>In multiple switch levels case, only the last level DSP should set BI Enable filed, other DSPs and root port should set BI Forward.
>
>But current implementation will set BI Enable on all DSPs, and set BI Forward on root port whatever the root port connects to BI-Capable device directly.
>
>If my understanding is incorrect, please let me know. thanks

Thanks for reviewing, I am just now circling back to this.

Yes, I think you are right. For v8 I have consolidated this for root ports and dsp,
the component directly attached to the device now always gets the Enable, the rest get FW.

Thanks,
Davidlohr

  reply	other threads:[~2026-09-03  1:24 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-28 14:41 [PATCH v7 0/8] cxl: Support Back-Invalidate Davidlohr Bueso
2026-07-28 14:41 ` [PATCH v7 1/8] cxl: Add BI register probing and port initialization Davidlohr Bueso
2026-08-04 21:13   ` Dave Jiang
2026-08-05  0:42   ` Alison Schofield
2026-08-05 10:41   ` Li Ming
2026-08-07  5:38   ` Richard Cheng
2026-08-09 20:06     ` Davidlohr Bueso
2026-07-28 14:41 ` [PATCH v7 2/8] cxl/pci: Add BI topology enable/disable Davidlohr Bueso
2026-07-28 15:16   ` sashiko-bot
2026-08-03 18:55     ` Davidlohr Bueso
2026-08-05 12:49   ` Li Ming
2026-08-05 13:33   ` Li Ming
2026-09-03  1:16     ` Davidlohr Bueso [this message]
2026-08-07  6:54   ` Richard Cheng
2026-09-03  0:12     ` Davidlohr Bueso
2026-07-28 14:41 ` [PATCH v7 3/8] cxl/hdm: Add BI coherency support for endpoint decoders Davidlohr Bueso
2026-07-28 15:26   ` sashiko-bot
2026-07-28 18:44     ` Davidlohr Bueso
2026-07-28 14:41 ` [PATCH v7 4/8] cxl: Add HDM-DB region creation Davidlohr Bueso
2026-08-04 22:28   ` Dave Jiang
2026-08-05  0:11   ` Alison Schofield
2026-08-05 19:10     ` Davidlohr Bueso
2026-08-07 11:50   ` Richard Cheng
2026-07-28 14:41 ` [PATCH v7 5/8] cxl/hdm: Rename decoder coherency flags Davidlohr Bueso
2026-08-05  1:13   ` Alison Schofield
2026-07-28 14:41 ` [PATCH v7 6/8] cxl/region: Log the coherency model at region creation Davidlohr Bueso
2026-08-04 22:51   ` Dave Jiang
2026-07-28 14:41 ` [PATCH v7 7/8] cxl/pci: Split BI capability probe from setup Davidlohr Bueso
2026-08-04 23:07   ` Dave Jiang
2026-07-28 14:41 ` [PATCH v7 8/8] cxl: Allow auto-committed BI hdm decoders Davidlohr Bueso
2026-07-28 15:46   ` sashiko-bot
2026-08-03 19:04     ` Davidlohr Bueso
2026-08-04 23:22   ` Dave Jiang
2026-08-05  0:51   ` Alison Schofield
2026-08-05 20:53     ` Davidlohr Bueso
2026-08-07 12:03   ` Richard Cheng
2026-09-03 18:58     ` Davidlohr Bueso

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