From: Alejandro Lucero Palau <alucerop@amd.com>
To: Alison Schofield <alison.schofield@intel.com>,
alejandro.lucero-palau@amd.com
Cc: linux-cxl@vger.kernel.org, netdev@vger.kernel.org,
dan.j.williams@intel.com, edward.cree@amd.com,
davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com,
edumazet@google.com, dave.jiang@intel.com,
Jonathan Cameron <Jonathan.Cameron@huawei.com>
Subject: Re: [PATCH v14 04/22] cxl: move register/capability check to driver
Date: Thu, 8 May 2025 14:13:07 +0100 [thread overview]
Message-ID: <3471f4dc-66f9-40b6-8934-b7d6e791e728@amd.com> (raw)
In-Reply-To: <aBwA_CI5-eNll6Iz@aschofie-mobl2.lan>
On 5/8/25 01:55, Alison Schofield wrote:
> On Thu, Apr 17, 2025 at 10:29:07PM +0100, alejandro.lucero-palau@amd.com wrote:
>> From: Alejandro Lucero <alucerop@amd.com>
>>
>> Type3 has some mandatory capabilities which are optional for Type2.
>>
>> In order to support same register/capability discovery code for both
>> types, avoid any assumption about what capabilities should be there, and
>> export the capabilities found for the caller doing the capabilities
>> check based on the expected ones.
>>
>> Add a function for facilitating the report of capabiities missing the
> sp. capabilities
>
I'll fix it.
>> expected ones.
>>
>> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> ---
>> drivers/cxl/core/pci.c | 35 +++++++++++++++++++++++++++++++++--
>> drivers/cxl/core/port.c | 8 ++++----
>> drivers/cxl/core/regs.c | 35 +++++++++++++++++++----------------
>> drivers/cxl/cxl.h | 6 +++---
>> drivers/cxl/cxlpci.h | 2 +-
>> drivers/cxl/pci.c | 24 +++++++++++++++++++++---
>> include/cxl/cxl.h | 24 ++++++++++++++++++++++++
>> 7 files changed, 105 insertions(+), 29 deletions(-)
>>
>> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
>> index 0b8dc34b8300..ed18260ff1c9 100644
>> --- a/drivers/cxl/core/pci.c
>> +++ b/drivers/cxl/core/pci.c
>> @@ -1061,7 +1061,7 @@ static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev,
>> }
>>
>> int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
>> - struct cxl_register_map *map)
>> + struct cxl_register_map *map, unsigned long *caps)
>> {
>> int rc;
>>
>> @@ -1091,7 +1091,7 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
>> return rc;
>> }
>>
>> - return cxl_setup_regs(map);
>> + return cxl_setup_regs(map, caps);
>> }
>> EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, "CXL");
>>
>> @@ -1214,3 +1214,34 @@ int cxl_gpf_port_setup(struct device *dport_dev, struct cxl_port *port)
>>
>> return 0;
>> }
>> +
>> +int cxl_check_caps(struct pci_dev *pdev, unsigned long *expected,
>> + unsigned long *found)
>> +{
>> + DECLARE_BITMAP(missing, CXL_MAX_CAPS);
>> +
>> + if (bitmap_subset(expected, found, CXL_MAX_CAPS))
>> + /* all good */
>> + return 0;
>> +
>> + bitmap_andnot(missing, expected, found, CXL_MAX_CAPS);
>> +
>> + if (test_bit(CXL_DEV_CAP_RAS, missing))
>> + dev_err(&pdev->dev, "RAS capability not found\n");
>> +
>> + if (test_bit(CXL_DEV_CAP_HDM, missing))
>> + dev_err(&pdev->dev, "HDM decoder capability not found\n");
>> +
>> + if (test_bit(CXL_DEV_CAP_DEV_STATUS, missing))
>> + dev_err(&pdev->dev, "Device Status capability not found\n");
>> +
>> + if (test_bit(CXL_DEV_CAP_MAILBOX_PRIMARY, missing))
>> + dev_err(&pdev->dev, "Primary Mailbox capability not found\n");
>> +
>> + if (test_bit(CXL_DEV_CAP_MEMDEV, missing))
>> + dev_err(&pdev->dev,
>> + "Memory Device Status capability not found\n");
>> +
>> + return -1;
>> +}
> Prefer using an array to map the enums to strings, like -
>
> static const char * const cap_names[CXL_MAX_CAPS] = {
> [CXL_DEV_CAP_RAS] = "CXL_DEV_CAP_RAS",
> .
> .
> .
> };
>
> and then loop thru that, like:
>
> for (int i = 0; i < CXL_MAX_CAPS; i++) {
> if (!test-bit(i, missing))
> dev_err(&pdev->dev,"%s capability not found\n",
> cap_names[i];
> }
>
Looks good to me and it saves some code lines. I'll do the change.
>
> snip
>> }
>> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
>> index be0ae9aca84a..e409ea06af0b 100644
>> --- a/drivers/cxl/core/regs.c
>> +++ b/drivers/cxl/core/regs.c
>> @@ -4,6 +4,7 @@
>> #include <linux/device.h>
>> #include <linux/slab.h>
>> #include <linux/pci.h>
>> +#include <cxl/cxl.h>
>> #include <cxl/pci.h>
>> #include <cxlmem.h>
>> #include <cxlpci.h>
>> @@ -11,6 +12,9 @@
>>
>> #include "core.h"
>>
>> +#define cxl_cap_set_bit(bit, caps) \
>> + do { if ((caps)) set_bit((bit), (caps)); } while (0)
>> +
> Prefer a readable and type safe simple fcn:
>
> static void cxl_cap_set_bit(int bit, unsigned long *caps)
> {
> if (caps)
> set_bit(bit, caps);
> }
>
I have no preference but I can do this change as well.
Thank you!
next prev parent reply other threads:[~2025-05-08 13:13 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-17 21:29 [PATCH v14 00/22] Type2 device basic support alejandro.lucero-palau
2025-04-17 21:29 ` [PATCH v14 01/22] cxl: add type2 " alejandro.lucero-palau
2025-05-07 14:37 ` Jonathan Cameron
2025-05-08 15:47 ` Alejandro Lucero Palau
2025-05-08 0:25 ` Alison Schofield
2025-05-08 10:19 ` Alejandro Lucero Palau
2025-04-17 21:29 ` [PATCH v14 02/22] sfc: add cxl support alejandro.lucero-palau
2025-05-07 14:42 ` Jonathan Cameron
2025-05-08 15:05 ` Edward Cree
2025-05-08 0:33 ` Alison Schofield
2025-05-08 12:41 ` Alejandro Lucero Palau
2025-05-08 17:12 ` Alison Schofield
2025-05-08 17:17 ` Alejandro Lucero Palau
2025-04-17 21:29 ` [PATCH v14 03/22] cxl: move pci generic code alejandro.lucero-palau
2025-05-08 0:36 ` Alison Schofield
2025-05-08 12:45 ` Alejandro Lucero Palau
2025-05-08 17:20 ` Alison Schofield
2025-05-08 17:20 ` Dave Jiang
2025-04-17 21:29 ` [PATCH v14 04/22] cxl: move register/capability check to driver alejandro.lucero-palau
2025-05-08 0:55 ` Alison Schofield
2025-05-08 13:13 ` Alejandro Lucero Palau [this message]
2025-04-17 21:29 ` [PATCH v14 05/22] cxl: add function for type2 cxl regs setup alejandro.lucero-palau
2025-05-07 14:47 ` Jonathan Cameron
2025-04-17 21:29 ` [PATCH v14 06/22] sfc: make regs setup with checking and set media ready alejandro.lucero-palau
2025-04-17 21:29 ` [PATCH v14 07/22] cxl: support dpa initialization without a mailbox alejandro.lucero-palau
2025-04-17 21:29 ` [PATCH v14 08/22] sfc: initialize dpa alejandro.lucero-palau
2025-05-07 14:49 ` Jonathan Cameron
2025-05-08 15:06 ` Edward Cree
2025-04-17 21:29 ` [PATCH v14 09/22] cxl: prepare memdev creation for type2 alejandro.lucero-palau
2025-05-08 1:06 ` Alison Schofield
2025-05-12 10:38 ` Alejandro Lucero Palau
2025-04-17 21:29 ` [PATCH v14 10/22] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-04-17 21:29 ` [PATCH v14 11/22] cxl: define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-04-22 16:22 ` Jonathan Cameron
2025-04-28 8:00 ` Alejandro Lucero Palau
2025-05-08 1:13 ` Alison Schofield
2025-05-08 14:09 ` Alejandro Lucero Palau
2025-05-08 17:31 ` Alison Schofield
2025-04-17 21:29 ` [PATCH v14 12/22] sfc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2025-04-17 21:29 ` [PATCH v14 13/22] cxl: define a driver interface for DPA allocation alejandro.lucero-palau
2025-05-08 18:02 ` Alison Schofield
2025-05-09 7:40 ` Alejandro Lucero Palau
2025-04-17 21:29 ` [PATCH v14 14/22] sfc: get endpoint decoder alejandro.lucero-palau
2025-04-17 21:29 ` [PATCH v14 15/22] cxl: make region type based on endpoint type alejandro.lucero-palau
2025-04-17 21:29 ` [PATCH v14 16/22] cxl/region: factor out interleave ways setup alejandro.lucero-palau
2025-05-08 1:16 ` Alison Schofield
2025-05-08 14:32 ` Alejandro Lucero Palau
2025-04-17 21:29 ` [PATCH v14 17/22] cxl/region: factor out interleave granularity setup alejandro.lucero-palau
2025-04-17 21:29 ` [PATCH v14 18/22] cxl: allow region creation by type2 drivers alejandro.lucero-palau
2025-04-17 21:29 ` [PATCH v14 19/22] cxl: add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2025-05-08 18:20 ` Alison Schofield
2025-05-09 8:16 ` Alejandro Lucero Palau
2025-04-17 21:29 ` [PATCH v14 20/22] sfc: create cxl region alejandro.lucero-palau
2025-04-17 21:29 ` [PATCH v14 21/22] cxl: add function for obtaining region range alejandro.lucero-palau
2025-05-08 1:24 ` Alison Schofield
2025-05-08 14:32 ` Alejandro Lucero Palau
2025-04-17 21:29 ` [PATCH v14 22/22] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-05-07 15:11 ` [PATCH v14 00/22] Type2 device basic support Jonathan Cameron
2025-05-08 1:59 ` Alison Schofield
2025-05-08 14:55 ` Alejandro Lucero Palau
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