From: Alejandro Lucero Palau <alucerop@amd.com>
To: Alison Schofield <alison.schofield@intel.com>,
alejandro.lucero-palau@amd.com
Cc: linux-cxl@vger.kernel.org, netdev@vger.kernel.org,
dan.j.williams@intel.com, edward.cree@amd.com,
davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com,
edumazet@google.com, dave.jiang@intel.com,
Zhi Wang <zhiw@nvidia.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Ben Cheatham <benjamin.cheatham@amd.com>
Subject: Re: [PATCH v14 16/22] cxl/region: factor out interleave ways setup
Date: Thu, 8 May 2025 15:32:12 +0100 [thread overview]
Message-ID: <53a199ba-8f17-4c38-8061-bf7c4f145fa1@amd.com> (raw)
In-Reply-To: <aBwGARkkDa1DmTkQ@aschofie-mobl2.lan>
On 5/8/25 02:16, Alison Schofield wrote:
> On Thu, Apr 17, 2025 at 10:29:19PM +0100, alejandro.lucero-palau@amd.com wrote:
>> From: Alejandro Lucero <alucerop@amd.com>
>>
>> In preparation for kernel driven region creation, factor out a common
> Please define "kernel driven region creation".
>
> Also, please keep repeating that these changes are introduced for Type 2
> support and note whether there is any functional change to existing region
> creation path.
Ok. I'll do so.
Thanks
>
>> helper from the user-sysfs region setup for interleave ways.
>>
>> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
>> Reviewed-by: Zhi Wang <zhiw@nvidia.com>
>> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
>> ---
>> drivers/cxl/core/region.c | 46 +++++++++++++++++++++++----------------
>> 1 file changed, 27 insertions(+), 19 deletions(-)
>
>> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
>> index 6371284283b0..095e52237516 100644
>> --- a/drivers/cxl/core/region.c
>> +++ b/drivers/cxl/core/region.c
>> @@ -464,22 +464,14 @@ static ssize_t interleave_ways_show(struct device *dev,
>>
>> static const struct attribute_group *get_cxl_region_target_group(void);
>>
>> -static ssize_t interleave_ways_store(struct device *dev,
>> - struct device_attribute *attr,
>> - const char *buf, size_t len)
>> +static int set_interleave_ways(struct cxl_region *cxlr, int val)
>> {
>> - struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev->parent);
>> + struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent);
>> struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
>> - struct cxl_region *cxlr = to_cxl_region(dev);
>> struct cxl_region_params *p = &cxlr->params;
>> - unsigned int val, save;
>> - int rc;
>> + int save, rc;
>> u8 iw;
>>
>> - rc = kstrtouint(buf, 0, &val);
>> - if (rc)
>> - return rc;
>> -
>> rc = ways_to_eiw(val, &iw);
>> if (rc)
>> return rc;
>> @@ -494,20 +486,36 @@ static ssize_t interleave_ways_store(struct device *dev,
>> return -EINVAL;
>> }
>>
>> - rc = down_write_killable(&cxl_region_rwsem);
>> - if (rc)
>> - return rc;
>> - if (p->state >= CXL_CONFIG_INTERLEAVE_ACTIVE) {
>> - rc = -EBUSY;
>> - goto out;
>> - }
>> + lockdep_assert_held_write(&cxl_region_rwsem);
>> + if (p->state >= CXL_CONFIG_INTERLEAVE_ACTIVE)
>> + return -EBUSY;
>>
>> save = p->interleave_ways;
>> p->interleave_ways = val;
>> rc = sysfs_update_group(&cxlr->dev.kobj, get_cxl_region_target_group());
>> if (rc)
>> p->interleave_ways = save;
>> -out:
>> +
>> + return rc;
>> +}
>> +
>> +static ssize_t interleave_ways_store(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf, size_t len)
>> +{
>> + struct cxl_region *cxlr = to_cxl_region(dev);
>> + unsigned int val;
>> + int rc;
>> +
>> + rc = kstrtouint(buf, 0, &val);
>> + if (rc)
>> + return rc;
>> +
>> + rc = down_write_killable(&cxl_region_rwsem);
>> + if (rc)
>> + return rc;
>> +
>> + rc = set_interleave_ways(cxlr, val);
>> up_write(&cxl_region_rwsem);
>> if (rc)
>> return rc;
>> --
>> 2.34.1
>>
>>
next prev parent reply other threads:[~2025-05-08 14:32 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-17 21:29 [PATCH v14 00/22] Type2 device basic support alejandro.lucero-palau
2025-04-17 21:29 ` [PATCH v14 01/22] cxl: add type2 " alejandro.lucero-palau
2025-05-07 14:37 ` Jonathan Cameron
2025-05-08 15:47 ` Alejandro Lucero Palau
2025-05-08 0:25 ` Alison Schofield
2025-05-08 10:19 ` Alejandro Lucero Palau
2025-04-17 21:29 ` [PATCH v14 02/22] sfc: add cxl support alejandro.lucero-palau
2025-05-07 14:42 ` Jonathan Cameron
2025-05-08 15:05 ` Edward Cree
2025-05-08 0:33 ` Alison Schofield
2025-05-08 12:41 ` Alejandro Lucero Palau
2025-05-08 17:12 ` Alison Schofield
2025-05-08 17:17 ` Alejandro Lucero Palau
2025-04-17 21:29 ` [PATCH v14 03/22] cxl: move pci generic code alejandro.lucero-palau
2025-05-08 0:36 ` Alison Schofield
2025-05-08 12:45 ` Alejandro Lucero Palau
2025-05-08 17:20 ` Alison Schofield
2025-05-08 17:20 ` Dave Jiang
2025-04-17 21:29 ` [PATCH v14 04/22] cxl: move register/capability check to driver alejandro.lucero-palau
2025-05-08 0:55 ` Alison Schofield
2025-05-08 13:13 ` Alejandro Lucero Palau
2025-04-17 21:29 ` [PATCH v14 05/22] cxl: add function for type2 cxl regs setup alejandro.lucero-palau
2025-05-07 14:47 ` Jonathan Cameron
2025-04-17 21:29 ` [PATCH v14 06/22] sfc: make regs setup with checking and set media ready alejandro.lucero-palau
2025-04-17 21:29 ` [PATCH v14 07/22] cxl: support dpa initialization without a mailbox alejandro.lucero-palau
2025-04-17 21:29 ` [PATCH v14 08/22] sfc: initialize dpa alejandro.lucero-palau
2025-05-07 14:49 ` Jonathan Cameron
2025-05-08 15:06 ` Edward Cree
2025-04-17 21:29 ` [PATCH v14 09/22] cxl: prepare memdev creation for type2 alejandro.lucero-palau
2025-05-08 1:06 ` Alison Schofield
2025-05-12 10:38 ` Alejandro Lucero Palau
2025-04-17 21:29 ` [PATCH v14 10/22] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-04-17 21:29 ` [PATCH v14 11/22] cxl: define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-04-22 16:22 ` Jonathan Cameron
2025-04-28 8:00 ` Alejandro Lucero Palau
2025-05-08 1:13 ` Alison Schofield
2025-05-08 14:09 ` Alejandro Lucero Palau
2025-05-08 17:31 ` Alison Schofield
2025-04-17 21:29 ` [PATCH v14 12/22] sfc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2025-04-17 21:29 ` [PATCH v14 13/22] cxl: define a driver interface for DPA allocation alejandro.lucero-palau
2025-05-08 18:02 ` Alison Schofield
2025-05-09 7:40 ` Alejandro Lucero Palau
2025-04-17 21:29 ` [PATCH v14 14/22] sfc: get endpoint decoder alejandro.lucero-palau
2025-04-17 21:29 ` [PATCH v14 15/22] cxl: make region type based on endpoint type alejandro.lucero-palau
2025-04-17 21:29 ` [PATCH v14 16/22] cxl/region: factor out interleave ways setup alejandro.lucero-palau
2025-05-08 1:16 ` Alison Schofield
2025-05-08 14:32 ` Alejandro Lucero Palau [this message]
2025-04-17 21:29 ` [PATCH v14 17/22] cxl/region: factor out interleave granularity setup alejandro.lucero-palau
2025-04-17 21:29 ` [PATCH v14 18/22] cxl: allow region creation by type2 drivers alejandro.lucero-palau
2025-04-17 21:29 ` [PATCH v14 19/22] cxl: add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2025-05-08 18:20 ` Alison Schofield
2025-05-09 8:16 ` Alejandro Lucero Palau
2025-04-17 21:29 ` [PATCH v14 20/22] sfc: create cxl region alejandro.lucero-palau
2025-04-17 21:29 ` [PATCH v14 21/22] cxl: add function for obtaining region range alejandro.lucero-palau
2025-05-08 1:24 ` Alison Schofield
2025-05-08 14:32 ` Alejandro Lucero Palau
2025-04-17 21:29 ` [PATCH v14 22/22] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-05-07 15:11 ` [PATCH v14 00/22] Type2 device basic support Jonathan Cameron
2025-05-08 1:59 ` Alison Schofield
2025-05-08 14:55 ` Alejandro Lucero Palau
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