Re: [PATCH ndctl 3/7] cxl: add core plumbing for creation of ram regions

["Verma, Vishal L" <vishal.l.verma@intel.com>]

On Fri, 2023-02-10 at 01:04 +0000, Fan Ni wrote:
> On Tue, Feb 07, 2023 at 12:16:29PM -0700, Vishal Verma wrote:
> > Add support in libcxl to create ram regions through a new
> > cxl_decoder_create_ram_region() API, which works similarly to its pmem
> > sibling.
> > 
> > Enable ram region creation in cxl-cli, with the only differences from
> > the pmem flow being:
> >   1/ Use the above create_ram_region API, and
> >   2/ Elide setting the UUID, since ram regions don't have one
> > 
> > Cc: Dan Williams <dan.j.williams@intel.com>
> > Signed-off-by: Vishal Verma <vishal.l.verma@intel.com>
> 
> Reviewed-by: Fan Ni <fan.ni@samsung.com>

Hi Fan,

Would you mind responding on v2 of this series - b4 doesn't want to
pick up trailers from v1 now that v2 has been sent out.

> 
> One minor thing, there exists some code format inconsistency in
> cxl/region.c file (not introduced by the patch). For exmaple,
> the "switch" sometimes is followed with a space but sometime not.

Ah thanks, I'll take a look and send separate cleanup patches.