From: Ira Weiny <ira.weiny@intel.com>
To: Vishal Verma <vishal.l.verma@intel.com>, <linux-cxl@vger.kernel.org>
Cc: Gregory Price <gregory.price@memverge.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Davidlohr Bueso <dave@stgolabs.net>,
"Dan Williams" <dan.j.williams@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>, <nvdimm@lists.linux.dev>
Subject: Re: [PATCH ndctl 2/7] cxl: add a type attribute to region listings
Date: Tue, 7 Feb 2023 19:46:58 -0800 [thread overview]
Message-ID: <63e31b32c80ff_107e3f2945c@iweiny-mobl.notmuch> (raw)
In-Reply-To: <20230120-vv-volatile-regions-v1-2-b42b21ee8d0b@intel.com>
Vishal Verma wrote:
> In preparation for enumerating and creating 'volatile' or 'ram' type
> regions, add a 'type' attribute to region listings, so these can be
> distinguished from 'pmem' type regions easily. This depends on a new
> 'mode' attribute for region objects in sysfs. For older kernels that
> lack this, region listings will simply omit emitting this attribute,
> but otherwise not treat it as a failure.
>
> Cc: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
> Signed-off-by: Vishal Verma <vishal.l.verma@intel.com>
> ---
> Documentation/cxl/lib/libcxl.txt | 1 +
> cxl/lib/private.h | 1 +
> cxl/lib/libcxl.c | 11 +++++++++++
> cxl/libcxl.h | 1 +
> cxl/json.c | 5 +++++
> cxl/lib/libcxl.sym | 5 +++++
> 6 files changed, 24 insertions(+)
>
> diff --git a/Documentation/cxl/lib/libcxl.txt b/Documentation/cxl/lib/libcxl.txt
> index f9af376..dbc4b56 100644
> --- a/Documentation/cxl/lib/libcxl.txt
> +++ b/Documentation/cxl/lib/libcxl.txt
> @@ -550,6 +550,7 @@ int cxl_region_get_id(struct cxl_region *region);
> const char *cxl_region_get_devname(struct cxl_region *region);
> void cxl_region_get_uuid(struct cxl_region *region, uuid_t uu);
> unsigned long long cxl_region_get_size(struct cxl_region *region);
> +enum cxl_decoder_mode cxl_region_get_mode(struct cxl_region *region);
> unsigned long long cxl_region_get_resource(struct cxl_region *region);
> unsigned int cxl_region_get_interleave_ways(struct cxl_region *region);
> unsigned int cxl_region_get_interleave_granularity(struct cxl_region *region);
> diff --git a/cxl/lib/private.h b/cxl/lib/private.h
> index f8871bd..306dc3a 100644
> --- a/cxl/lib/private.h
> +++ b/cxl/lib/private.h
> @@ -149,6 +149,7 @@ struct cxl_region {
> unsigned int interleave_ways;
> unsigned int interleave_granularity;
> enum cxl_decode_state decode_state;
> + enum cxl_decoder_mode mode;
> struct kmod_module *module;
> struct list_head mappings;
> };
> diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c
> index 4205a58..83f628b 100644
> --- a/cxl/lib/libcxl.c
> +++ b/cxl/lib/libcxl.c
> @@ -561,6 +561,12 @@ static void *add_cxl_region(void *parent, int id, const char *cxlregion_base)
> else
> region->decode_state = strtoul(buf, NULL, 0);
>
> + sprintf(path, "%s/mode", cxlregion_base);
> + if (sysfs_read_attr(ctx, path, buf) < 0)
> + region->mode = CXL_DECODER_MODE_NONE;
> + else
> + region->mode = cxl_decoder_mode_from_ident(buf);
> +
> sprintf(path, "%s/modalias", cxlregion_base);
> if (sysfs_read_attr(ctx, path, buf) == 0)
> region->module = util_modalias_to_module(ctx, buf);
> @@ -686,6 +692,11 @@ CXL_EXPORT unsigned long long cxl_region_get_resource(struct cxl_region *region)
> return region->start;
> }
>
> +CXL_EXPORT enum cxl_decoder_mode cxl_region_get_mode(struct cxl_region *region)
> +{
> + return region->mode;
> +}
> +
> CXL_EXPORT unsigned int
> cxl_region_get_interleave_ways(struct cxl_region *region)
> {
> diff --git a/cxl/libcxl.h b/cxl/libcxl.h
> index d699af8..e6cca11 100644
> --- a/cxl/libcxl.h
> +++ b/cxl/libcxl.h
> @@ -273,6 +273,7 @@ const char *cxl_region_get_devname(struct cxl_region *region);
> void cxl_region_get_uuid(struct cxl_region *region, uuid_t uu);
> unsigned long long cxl_region_get_size(struct cxl_region *region);
> unsigned long long cxl_region_get_resource(struct cxl_region *region);
> +enum cxl_decoder_mode cxl_region_get_mode(struct cxl_region *region);
> unsigned int cxl_region_get_interleave_ways(struct cxl_region *region);
> unsigned int cxl_region_get_interleave_granularity(struct cxl_region *region);
> struct cxl_decoder *cxl_region_get_target_decoder(struct cxl_region *region,
> diff --git a/cxl/json.c b/cxl/json.c
> index 0fc44e4..f625380 100644
> --- a/cxl/json.c
> +++ b/cxl/json.c
> @@ -827,6 +827,7 @@ void util_cxl_mappings_append_json(struct json_object *jregion,
> struct json_object *util_cxl_region_to_json(struct cxl_region *region,
> unsigned long flags)
> {
> + enum cxl_decoder_mode mode = cxl_region_get_mode(region);
> const char *devname = cxl_region_get_devname(region);
> struct json_object *jregion, *jobj;
> u64 val;
> @@ -853,6 +854,10 @@ struct json_object *util_cxl_region_to_json(struct cxl_region *region,
> json_object_object_add(jregion, "size", jobj);
> }
>
> + jobj = json_object_new_string(cxl_decoder_mode_name(mode));
> + if (jobj)
> + json_object_object_add(jregion, "type", jobj);
> +
> val = cxl_region_get_interleave_ways(region);
> if (val < INT_MAX) {
> jobj = json_object_new_int(val);
> diff --git a/cxl/lib/libcxl.sym b/cxl/lib/libcxl.sym
> index 6bc0810..9832d09 100644
> --- a/cxl/lib/libcxl.sym
> +++ b/cxl/lib/libcxl.sym
> @@ -242,3 +242,8 @@ global:
> cxl_target_get_firmware_node;
> cxl_dport_get_firmware_node;
> } LIBCXL_3;
> +
> +LIBCXL_5 {
> +global:
> + cxl_region_get_mode;
> +} LIBCXL_4;
>
> --
> 2.39.1
>
next prev parent reply other threads:[~2023-02-08 3:48 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-07 19:16 [PATCH ndctl 0/7] cxl: add support for listing and creating volatile regions Vishal Verma
2023-02-07 19:16 ` [PATCH ndctl 1/7] cxl/region: skip region_actions for region creation Vishal Verma
2023-02-07 22:07 ` Fan Ni
2023-02-08 0:19 ` Verma, Vishal L
2023-02-08 3:45 ` Ira Weiny
2023-02-08 5:41 ` Dan Williams
2023-02-07 19:16 ` [PATCH ndctl 2/7] cxl: add a type attribute to region listings Vishal Verma
2023-02-08 3:46 ` Ira Weiny [this message]
2023-02-08 5:47 ` Dan Williams
2023-02-08 6:10 ` Verma, Vishal L
2023-02-10 0:47 ` Fan Ni
2023-02-07 19:16 ` [PATCH ndctl 3/7] cxl: add core plumbing for creation of ram regions Vishal Verma
2023-02-08 3:55 ` Ira Weiny
2023-02-08 6:23 ` Verma, Vishal L
2023-02-08 22:07 ` Ira Weiny
2023-02-08 5:49 ` Dan Williams
2023-02-10 1:04 ` Fan Ni
2023-02-10 1:10 ` Verma, Vishal L
2023-02-10 1:15 ` Fan Ni
2023-02-07 19:16 ` [PATCH ndctl 4/7] cxl/region: accept user-supplied UUIDs for pmem regions Vishal Verma
2023-02-08 3:56 ` Ira Weiny
2023-02-08 5:51 ` Dan Williams
2023-02-07 19:16 ` [PATCH ndctl 5/7] cxl/region: determine region type based on root decoder capability Vishal Verma
2023-02-08 4:07 ` Ira Weiny
2023-02-08 6:34 ` Verma, Vishal L
2023-02-08 22:09 ` Ira Weiny
2023-02-08 5:55 ` Dan Williams
2023-02-08 6:36 ` Verma, Vishal L
2023-02-07 19:16 ` [PATCH ndctl 6/7] cxl/list: Include regions in the verbose listing Vishal Verma
2023-02-08 4:08 ` Ira Weiny
2023-02-07 19:16 ` [PATCH ndctl 7/7] cxl/list: Enumerate device-dax properties for regions Vishal Verma
2023-02-08 4:15 ` Ira Weiny
2023-02-08 6:00 ` Dan Williams
2023-02-08 6:48 ` Verma, Vishal L
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