Re: [PATCH v3 3/3] Add function to display cxl1.1 device link status

[Dan Williams <dan.j.williams@intel.com>]

Martin Mareš wrote:
[..]
> 
> This really is not the right place to read from sysfs. The libpci should provide
> a backend-indepenent interface for reading this information and the sysfs
> back-end (lib/sysfs.c) should provide one implementation of this interface.
> 
> I think that we can easily extend pci_fill_info() and add another PCI_FILL_xxx
> flag for CXL RCD properties, which will be available in struct pci_dev (beware
> that new fields have to be added _after_ all public fields to keep ABI compatibility).
> 
> > @@ -1445,6 +1515,9 @@ cap_express(struct device *d, int where, int cap)
> >    cap_express_dev(d, where, type);
> >    if (link)
> >      cap_express_link(d, where, type);
> > +  else if (type == PCI_EXP_TYPE_ROOT_INT_EP)
> > +    cap_express_link_rcd(d);
> > +   
> >    if (slot)
> >      cap_express_slot(d, where);
> >    if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
> 
> Does it make sense to look up CXL RCD information for all PCIe devices of type
> PCI_EXP_TYPE_ROOT_INT_EP? Shouldn't it be done only for devices with the CXL
> capability?

I think so, would this fit more naturally in pci_scan_caps() with a new
scan for DVSEC caps ("PCI_EXT_CAP_ID_DVSEC" in Linux). However, isn't
the trouble that this needs a DVSEC scan for CXL to know it needs to go
back and fill in details that normally in appear in the base PCIe
capability scan?