Re: [PATCH 2/4] cxl: Introduce to_{ram,pmem}_{res,perf}() helpers

[Dan Williams <dan.j.williams@intel.com>]

Jonathan Cameron wrote:
> On Fri, 17 Jan 2025 10:20:56 +0000
> Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote:
> 
> > On Thu, 16 Jan 2025 22:10:38 -0800
> > Dan Williams <dan.j.williams@intel.com> wrote:
> > 
> > > In preparation for consolidating all DPA partition information into an
> > > array of DPA metadata, introduce helpers that hide the layout of the
> > > current data. I.e. make the eventual replacement of ->ram_res,  
> > > ->pmem_res, ->ram_perf, and ->pmem_perf with a new DPA metadata array a    
> > > no-op for code paths that consume that information, and reduce the noise
> > > of follow-on patches.
> > > 
> > > The end goal is to consolidate all DPA information in 'struct
> > > cxl_dev_state', but for now the helpers just make it appear that all DPA
> > > metadata is relative to @cxlds.
> > > 
> > > Note that a follow-on patch also cleans up the temporary placeholders of
> > > @ram_res, and @pmem_res in the qos_class manipulation code,
> > > cxl_dpa_alloc(), and cxl_mem_create_range_info().
> > > 
> > > Cc: Dave Jiang <dave.jiang@intel.com>
> > > Cc: Alejandro Lucero <alucerop@amd.com>
> > > Cc: Ira Weiny <ira.weiny@intel.com>
> > > Signed-off-by: Dan Williams <dan.j.williams@intel.com>  
> > 
> > I'm not that keen on wrapping the size but not the base.
> > Leads to some odd looking code in places.
> 
> I seems some of the code I didn't like goes away anyway later in the series.
> So maybe it makes sense from a churn reduction point of view.

Yeah, I tried to clarify that was a temporary side effect of patch
splitting until 'struct cxl_dpa_partition' could clean things up
further.