Re: [PATCH 0/4] cxl: Delay HB port and switch dport probing until endpoint dev probe

[Dave Jiang <dave.jiang@intel.com>]

On 4/10/25 8:05 PM, Li Ming wrote:
> On 4/5/2025 6:57 AM, Dave Jiang wrote:
>> This series attempts to delay the setup of dports and Host Bridge (HB) register
>> probing until when the endpoint device (memdev) is being probed. At this point,
>> the CXL link is established and all the devices along the CXL link path up to
>> the Root Port (RP) should be active.
>>
>> And hopefully this help a bit with Robert's issue raised in the "Inactive
>> downstream port handling" series [1]. Testing would be appreicated. Thank you!
>>
>> [1]: https://lore.kernel.org/linux-cxl/67c8a0cc23ec_24b64294f6@dwillia2-xfh.jf.intel.com.notmuch/
> 
> Hi Dave,
> 
> Thanks for that, you can also mention the patchset is also a long term solution for the issue[2]
> 
> [2]: https://lore.kernel.org/linux-cxl/6712b7bf2c1cd_10a03294b3@dwillia2-mobl3.amr.corp.intel.com.notmuch/
> 
> 
> After going through the implementation, Setup component registers is triggered on root port and HB when the first endpoint under them attaching, then component registers information are cached. But the information will not be reset after the last endpoint under the root port and HB removed. So the information will be resued when an new endpoint is re-attached to the root port and HB.
> 
> I am not sure if component registers information on hardware side is possible to be changed in above case. Just want to know if we need to consider about it?

I do not know either and I don't have the hotplug hardware to see. Unless someone can report the behavior, it may be one of those we cross that bridge when we get there situation.

> 
> 
> Ming
>