* [PATCH qemu v4 0/5] cxl: r3.2 specification event updates.
@ 2026-01-19 11:15 Jonathan Cameron
2026-01-19 11:15 ` [PATCH qemu v4 1/5] qapi: cxl: Refactor CXL event injection for common commands arguments Jonathan Cameron
` (5 more replies)
0 siblings, 6 replies; 13+ messages in thread
From: Jonathan Cameron @ 2026-01-19 11:15 UTC (permalink / raw)
To: Michael Tsirkin, qemu-devel, shiju.jose, armbru
Cc: linuxarm, linux-cxl, Ravi Shankar
Chances since v3:
https://lore.kernel.org/qemu-devel/20260114142713.617806-1-Jonathan.Cameron@huawei.com/
Update references in the documentation for related commands as well as the
structures. (Markus)
Changes since v2:
https://lore.kernel.org/all/20260102151512.460766-1-Jonathan.Cameron@huawei.com/
Thanks to Markus Armbruster.
- Expand LD acronym. Given the spec definition is acronyms soup, just
expand to Logical Device and let people go enjoy the specification if
they want to know what that actually means!
- Update spec references elsewhere in the qapi commands and data types
so they all refer to r3.2 rather than just the new bits.
v2: Cover letter,
Hi Michael,
This is a rebase/resend of:
https://lore.kernel.org/qemu-devel/20250917141355.293217-1-Jonathan.Cameron@huawei.com/
which I think slipped through the cracks for 10.2.
Original cover letter:
This is the 1st CXL set that I think is ready for upstream.
They are lightly tweaked and rebased from the first part of:
https://lore.kernel.org/qemu-devel/20250811085530.2263-1-shiju.jose@huawei.com/
[PATCH v6 0/8] hw/cxl: Update CXL events to rev3.2 and add maintenance support for memory repair features
I've split that series up as the two parts were only slightly connected.
The initial rework was a request from Markus from an earlier version.
Shiju Jose (5):
Shiju Jose (5):
qapi: cxl: Refactor CXL event injection for common commands arguments
hw/cxl/events: Update for rev3.2 common event record format
hw/cxl/events: Updates for rev3.2 general media event record
hw/cxl/events: Updates for rev3.2 DRAM event record
hw/cxl/events: Updates for rev3.2 memory module event record
qapi/cxl.json | 180 ++++++++++++++++++++++++++----------
include/hw/cxl/cxl_device.h | 7 +-
include/hw/cxl/cxl_events.h | 38 ++++++--
hw/cxl/cxl-events.c | 3 +-
hw/cxl/cxl-mailbox-utils.c | 3 +-
hw/mem/cxl_type3.c | 163 ++++++++++++++++++++++++++++++--
hw/mem/cxl_type3_stubs.c | 41 +++++++-
7 files changed, 362 insertions(+), 73 deletions(-)
--
2.48.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH qemu v4 1/5] qapi: cxl: Refactor CXL event injection for common commands arguments
2026-01-19 11:15 [PATCH qemu v4 0/5] cxl: r3.2 specification event updates Jonathan Cameron
@ 2026-01-19 11:15 ` Jonathan Cameron
2026-02-04 21:34 ` Ravi Jonnalagadda
2026-01-19 11:15 ` [PATCH qemu v4 2/5] hw/cxl/events: Update for rev3.2 common event record format Jonathan Cameron
` (4 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Jonathan Cameron @ 2026-01-19 11:15 UTC (permalink / raw)
To: Michael Tsirkin, qemu-devel, shiju.jose, armbru
Cc: linuxarm, linux-cxl, Ravi Shankar
From: Shiju Jose <shiju.jose@huawei.com>
Refactor CXL event injection to use struct for common command
arguments.
Suggested-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
v3: Fix wrong comment for memory module event (Markus)
---
qapi/cxl.json | 89 +++++++++++++++++++++++++++++++++------------------
1 file changed, 58 insertions(+), 31 deletions(-)
diff --git a/qapi/cxl.json b/qapi/cxl.json
index eeddb58d1d3f..55a088586e53 100644
--- a/qapi/cxl.json
+++ b/qapi/cxl.json
@@ -31,11 +31,10 @@
}
##
-# @cxl-inject-general-media-event:
+# @CXLCommonEventBase:
#
-# Inject an event record for a General Media Event (CXL r3.0
-# 8.2.9.2.1.1). This event type is reported via one of the event logs
-# specified via the log parameter.
+# Common event base for a CXL Event (CXL r3.0 8.2.9.2.1
+# Table 8-42 Common Event Record Format).
#
# @path: CXL type 3 device canonical QOM path
#
@@ -44,6 +43,16 @@
# @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
# Record Format, Event Record Flags for subfield definitions.
#
+# Since: 8.1
+##
+{ 'struct': 'CXLCommonEventBase',
+ 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8' } }
+
+##
+# @CXLGeneralMediaEvent:
+#
+# Event record for a General Media Event (CXL r3.0 8.2.9.2.1.1).
+#
# @dpa: Device Physical Address (relative to @path device). Note
# lower bits include some flags. See CXL r3.0 Table 8-43 General
# Media Event Record, Physical Address.
@@ -74,26 +83,29 @@
#
# Since: 8.1
##
-{ 'command': 'cxl-inject-general-media-event',
- 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8',
- 'dpa': 'uint64', 'descriptor': 'uint8',
+{ 'struct': 'CXLGeneralMediaEvent',
+ 'base': 'CXLCommonEventBase',
+ 'data': { 'dpa': 'uint64', 'descriptor': 'uint8',
'type': 'uint8', 'transaction-type': 'uint8',
'*channel': 'uint8', '*rank': 'uint8',
'*device': 'uint32', '*component-id': 'str' } }
##
-# @cxl-inject-dram-event:
-#
-# Inject an event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
-# This event type is reported via one of the event logs specified via
-# the log parameter.
+# @cxl-inject-general-media-event:
#
-# @path: CXL type 3 device canonical QOM path
+# Inject an event record for a General Media Event (CXL r3.0
+# 8.2.9.2.1.1). This event type is reported via one of the event
+# logs specified via the log parameter.
#
-# @log: Event log to add the event to
+# Since: 8.1
+##
+{ 'command': 'cxl-inject-general-media-event',
+ 'data': 'CXLGeneralMediaEvent' }
+
+##
+# @CXLDRAMEvent:
#
-# @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
-# Record Format, Event Record Flags for subfield definitions.
+# Event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
#
# @dpa: Device Physical Address (relative to @path device). Note
# lower bits include some flags. See CXL r3.0 Table 8-44 DRAM
@@ -133,9 +145,9 @@
#
# Since: 8.1
##
-{ 'command': 'cxl-inject-dram-event',
- 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8',
- 'dpa': 'uint64', 'descriptor': 'uint8',
+{ 'struct': 'CXLDRAMEvent',
+ 'base': 'CXLCommonEventBase',
+ 'data': { 'dpa': 'uint64', 'descriptor': 'uint8',
'type': 'uint8', 'transaction-type': 'uint8',
'*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32',
'*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32',
@@ -143,18 +155,21 @@
}}
##
-# @cxl-inject-memory-module-event:
-#
-# Inject an event record for a Memory Module Event (CXL r3.0
-# 8.2.9.2.1.3). This event includes a copy of the Device Health info
-# at the time of the event.
+# @cxl-inject-dram-event:
#
-# @path: CXL type 3 device canonical QOM path
+# Inject an event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
+# This event type is reported via one of the event logs
+# specified via the log parameter.
#
-# @log: Event Log to add the event to
+# Since: 8.1
+##
+{ 'command': 'cxl-inject-dram-event',
+ 'data': 'CXLDRAMEvent' }
+
+##
+# @CXLMemModuleEvent:
#
-# @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
-# Record Format, Event Record Flags for subfield definitions.
+# Event record for a Memory Module Event (CXL r3.0 8.2.9.2.1.3).
#
# @type: Device Event Type. See CXL r3.0 Table 8-45 Memory Module
# Event Record for bit definitions for bit definiions.
@@ -185,9 +200,9 @@
#
# Since: 8.1
##
-{ 'command': 'cxl-inject-memory-module-event',
- 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags' : 'uint8',
- 'type': 'uint8', 'health-status': 'uint8',
+{ 'struct': 'CXLMemModuleEvent',
+ 'base': 'CXLCommonEventBase',
+ 'data': { 'type': 'uint8', 'health-status': 'uint8',
'media-status': 'uint8', 'additional-status': 'uint8',
'life-used': 'uint8', 'temperature' : 'int16',
'dirty-shutdown-count': 'uint32',
@@ -195,6 +210,18 @@
'corrected-persistent-error-count': 'uint32'
}}
+##
+# @cxl-inject-memory-module-event:
+#
+# Inject an event record for a Memory Module Event (CXL r3.0
+# 8.2.9.2.1.3). This event includes a copy of the Device Health info
+# at the time of the event.
+#
+# Since: 8.1
+##
+{ 'command': 'cxl-inject-memory-module-event',
+ 'data': 'CXLMemModuleEvent' }
+
##
# @cxl-inject-poison:
#
--
2.48.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH qemu v4 2/5] hw/cxl/events: Update for rev3.2 common event record format
2026-01-19 11:15 [PATCH qemu v4 0/5] cxl: r3.2 specification event updates Jonathan Cameron
2026-01-19 11:15 ` [PATCH qemu v4 1/5] qapi: cxl: Refactor CXL event injection for common commands arguments Jonathan Cameron
@ 2026-01-19 11:15 ` Jonathan Cameron
2026-02-04 21:35 ` Ravi Jonnalagadda
2026-01-19 11:15 ` [PATCH qemu v4 3/5] hw/cxl/events: Updates for rev3.2 general media event record Jonathan Cameron
` (3 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Jonathan Cameron @ 2026-01-19 11:15 UTC (permalink / raw)
To: Michael Tsirkin, qemu-devel, shiju.jose, armbru
Cc: linuxarm, linux-cxl, Ravi Shankar
From: Shiju Jose <shiju.jose@huawei.com>
CXL spec 3.2 section 8.2.9.2.1 Table 8-55, Common Event Record
format has updated with optional Maintenance Operation Subclass,
LD ID and ID of the device head information.
Add updates for the above optional parameters in the related
CXL events reporting and in the QMP commands to inject CXL events.
Update all related specification references to CXL r3.2 to ensure
one consistent source.
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
v3: Expand the LD acronym (Markus)
---
qapi/cxl.json | 21 ++++++++---
include/hw/cxl/cxl_device.h | 7 +++-
include/hw/cxl/cxl_events.h | 15 ++++++--
hw/cxl/cxl-events.c | 3 +-
hw/cxl/cxl-mailbox-utils.c | 3 +-
hw/mem/cxl_type3.c | 70 ++++++++++++++++++++++++++++++++-----
hw/mem/cxl_type3_stubs.c | 24 +++++++++++--
7 files changed, 122 insertions(+), 21 deletions(-)
diff --git a/qapi/cxl.json b/qapi/cxl.json
index 55a088586e53..82001c0591d8 100644
--- a/qapi/cxl.json
+++ b/qapi/cxl.json
@@ -33,20 +33,33 @@
##
# @CXLCommonEventBase:
#
-# Common event base for a CXL Event (CXL r3.0 8.2.9.2.1
-# Table 8-42 Common Event Record Format).
+# Common event base for a CXL Event (CXL r3.2 8.2.10.2.1
+# Table 8-55 Common Event Record Format).
#
# @path: CXL type 3 device canonical QOM path
#
# @log: event log to add the event to
#
-# @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
+# @flags: Event Record Flags. See CXL r3.2 Table 8-55 Common Event
# Record Format, Event Record Flags for subfield definitions.
#
+# @maint-op-class: Maintenance operation class the device requests to
+# initiate.
+#
+# @maint-op-subclass: Maintenance operation subclass the device
+# requests to initiate.
+#
+# @ld-id: Logical Device (LD) ID of LD from where the event
+# originated.
+#
+# @head-id: ID of the device head from where the event originated.
+#
# Since: 8.1
##
{ 'struct': 'CXLCommonEventBase',
- 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8' } }
+ 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint32',
+ '*maint-op-class':'uint8', '*maint-op-subclass':'uint8',
+ '*ld-id':'uint16', '*head-id':'uint8' } }
##
# @CXLGeneralMediaEvent:
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index 165355baf9da..e461a824b692 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -723,7 +723,12 @@ bool ct3_test_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa,
uint64_t len);
void cxl_assign_event_header(CXLEventRecordHdr *hdr,
const QemuUUID *uuid, uint32_t flags,
- uint8_t length, uint64_t timestamp);
+ uint8_t length, uint64_t timestamp,
+ bool has_maint_op_class, uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id);
void cxl_create_dc_event_records_for_extents(CXLType3Dev *ct3d,
CXLDCEventType type,
CXLDCExtentRaw extents[],
diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h
index 758b075a64b9..4d9cfdb621ea 100644
--- a/include/hw/cxl/cxl_events.h
+++ b/include/hw/cxl/cxl_events.h
@@ -29,9 +29,15 @@ typedef enum CXLEventLogType {
/*
* Common Event Record Format
- * CXL r3.1 section 8.2.9.2.1: Event Records; Table 8-43
+ * CXL r3.2 section 8.2.10.2.1: Event Records; Table 8-55
*/
-#define CXL_EVENT_REC_HDR_RES_LEN 0xf
+#define CXL_EVENT_REC_FLAGS_PERMANENT_COND BIT(2)
+#define CXL_EVENT_REC_FLAGS_MAINT_NEEDED BIT(3)
+#define CXL_EVENT_REC_FLAGS_PERF_DEGRADED BIT(4)
+#define CXL_EVENT_REC_FLAGS_HW_REPLACEMENT_NEEDED BIT(5)
+#define CXL_EVENT_REC_FLAGS_MAINT_OP_SUBCLASS_VALID BIT(6)
+#define CXL_EVENT_REC_FLAGS_LD_ID_VALID BIT(7)
+#define CXL_EVENT_REC_FLAGS_HEAD_ID_VALID BIT(8)
typedef struct CXLEventRecordHdr {
QemuUUID id;
uint8_t length;
@@ -40,7 +46,10 @@ typedef struct CXLEventRecordHdr {
uint16_t related_handle;
uint64_t timestamp;
uint8_t maint_op_class;
- uint8_t reserved[CXL_EVENT_REC_HDR_RES_LEN];
+ uint8_t maint_op_subclass;
+ uint16_t ld_id;
+ uint8_t head_id;
+ uint8_t reserved[0xb];
} QEMU_PACKED CXLEventRecordHdr;
#define CXL_EVENT_RECORD_DATA_LENGTH 0x50
diff --git a/hw/cxl/cxl-events.c b/hw/cxl/cxl-events.c
index 7583dd9162f6..5356dfb5b300 100644
--- a/hw/cxl/cxl-events.c
+++ b/hw/cxl/cxl-events.c
@@ -271,7 +271,8 @@ void cxl_create_dc_event_records_for_extents(CXLType3Dev *ct3d,
&dynamic_capacity_uuid,
(1 << CXL_EVENT_TYPE_INFO),
sizeof(event_rec),
- cxl_device_get_timestamp(&ct3d->cxl_dstate));
+ cxl_device_get_timestamp(&ct3d->cxl_dstate),
+ 0, 0, 0, 0, 0, 0, 0, 0);
event_rec.type = type;
event_rec.validity_flags = 1;
event_rec.host_id = 0;
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index 6cfdd98168f9..e9528da70cc4 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -3458,7 +3458,8 @@ static CXLRetCode cmd_fm_set_dc_region_config(const struct cxl_cmd *cmd,
&dynamic_capacity_uuid,
(1 << CXL_EVENT_TYPE_INFO),
sizeof(dcEvent),
- cxl_device_get_timestamp(&ct3d->cxl_dstate));
+ cxl_device_get_timestamp(&ct3d->cxl_dstate),
+ 0, 0, 0, 0, 0, 0, 0, 0);
dcEvent.type = DC_EVENT_REGION_CONFIG_UPDATED;
dcEvent.validity_flags = 1;
dcEvent.host_id = 0;
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 6eb20137a04f..371bd4dc6ab2 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -1592,12 +1592,39 @@ void qmp_cxl_inject_correctable_error(const char *path, CxlCorErrorType type,
void cxl_assign_event_header(CXLEventRecordHdr *hdr,
const QemuUUID *uuid, uint32_t flags,
- uint8_t length, uint64_t timestamp)
+ uint8_t length, uint64_t timestamp,
+ bool has_maint_op_class, uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id)
{
- st24_le_p(&hdr->flags, flags);
hdr->length = length;
memcpy(&hdr->id, uuid, sizeof(hdr->id));
stq_le_p(&hdr->timestamp, timestamp);
+
+ if (has_maint_op_class) {
+ hdr->maint_op_class = maint_op_class;
+ } else {
+ hdr->maint_op_class = 0;
+ }
+
+ if (has_maint_op_subclass) {
+ flags |= CXL_EVENT_REC_FLAGS_MAINT_OP_SUBCLASS_VALID;
+ hdr->maint_op_subclass = maint_op_subclass;
+ }
+
+ if (has_ld_id) {
+ flags |= CXL_EVENT_REC_FLAGS_LD_ID_VALID;
+ stw_le_p(&hdr->ld_id, ld_id);
+ }
+
+ if (has_head_id) {
+ flags |= CXL_EVENT_REC_FLAGS_HEAD_ID_VALID;
+ hdr->head_id = head_id;
+ }
+
+ st24_le_p(&hdr->flags, flags);
}
static const QemuUUID gen_media_uuid = {
@@ -1637,7 +1664,13 @@ static int ct3d_qmp_cxl_event_log_enc(CxlEventLog log)
}
/* Component ID is device specific. Define this as a string. */
void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
- uint8_t flags, uint64_t dpa,
+ uint32_t flags, bool has_maint_op_class,
+ uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id,
+ uint64_t dpa,
uint8_t descriptor, uint8_t type,
uint8_t transaction_type,
bool has_channel, uint8_t channel,
@@ -1675,7 +1708,10 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
memset(&gem, 0, sizeof(gem));
cxl_assign_event_header(hdr, &gen_media_uuid, flags, sizeof(gem),
- cxl_device_get_timestamp(&ct3d->cxl_dstate));
+ cxl_device_get_timestamp(&ct3d->cxl_dstate),
+ has_maint_op_class, maint_op_class,
+ has_maint_op_subclass, maint_op_subclass,
+ has_ld_id, ld_id, has_head_id, head_id);
stq_le_p(&gem.phys_addr, dpa);
gem.descriptor = descriptor;
@@ -1719,7 +1755,13 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
#define CXL_DRAM_VALID_COLUMN BIT(6)
#define CXL_DRAM_VALID_CORRECTION_MASK BIT(7)
-void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
+void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
+ uint32_t flags,
+ bool has_maint_op_class, uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id,
uint64_t dpa, uint8_t descriptor,
uint8_t type, uint8_t transaction_type,
bool has_channel, uint8_t channel,
@@ -1762,7 +1804,10 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
memset(&dram, 0, sizeof(dram));
cxl_assign_event_header(hdr, &dram_uuid, flags, sizeof(dram),
- cxl_device_get_timestamp(&ct3d->cxl_dstate));
+ cxl_device_get_timestamp(&ct3d->cxl_dstate),
+ has_maint_op_class, maint_op_class,
+ has_maint_op_subclass, maint_op_subclass,
+ has_ld_id, ld_id, has_head_id, head_id);
stq_le_p(&dram.phys_addr, dpa);
dram.descriptor = descriptor;
dram.type = type;
@@ -1822,7 +1867,13 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
}
void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
- uint8_t flags, uint8_t type,
+ uint32_t flags, bool has_maint_op_class,
+ uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id,
+ uint8_t type,
uint8_t health_status,
uint8_t media_status,
uint8_t additional_status,
@@ -1861,7 +1912,10 @@ void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
memset(&module, 0, sizeof(module));
cxl_assign_event_header(hdr, &memory_module_uuid, flags, sizeof(module),
- cxl_device_get_timestamp(&ct3d->cxl_dstate));
+ cxl_device_get_timestamp(&ct3d->cxl_dstate),
+ has_maint_op_class, maint_op_class,
+ has_maint_op_subclass, maint_op_subclass,
+ has_ld_id, ld_id, has_head_id, head_id);
module.type = type;
module.health_status = health_status;
diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c
index c1a5e4a7c193..91b1478114d9 100644
--- a/hw/mem/cxl_type3_stubs.c
+++ b/hw/mem/cxl_type3_stubs.c
@@ -14,7 +14,13 @@
#include "qapi/qapi-commands-cxl.h"
void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
- uint8_t flags, uint64_t dpa,
+ uint32_t flags, bool has_maint_op_class,
+ uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id,
+ uint64_t dpa,
uint8_t descriptor, uint8_t type,
uint8_t transaction_type,
bool has_channel, uint8_t channel,
@@ -23,7 +29,13 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
const char *component_id,
Error **errp) {}
-void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
+void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
+ uint32_t flags,
+ bool has_maint_op_class, uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id,
uint64_t dpa, uint8_t descriptor,
uint8_t type, uint8_t transaction_type,
bool has_channel, uint8_t channel,
@@ -38,7 +50,13 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
Error **errp) {}
void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
- uint8_t flags, uint8_t type,
+ uint32_t flags, bool has_maint_op_class,
+ uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id,
+ uint8_t type,
uint8_t health_status,
uint8_t media_status,
uint8_t additional_status,
--
2.48.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH qemu v4 3/5] hw/cxl/events: Updates for rev3.2 general media event record
2026-01-19 11:15 [PATCH qemu v4 0/5] cxl: r3.2 specification event updates Jonathan Cameron
2026-01-19 11:15 ` [PATCH qemu v4 1/5] qapi: cxl: Refactor CXL event injection for common commands arguments Jonathan Cameron
2026-01-19 11:15 ` [PATCH qemu v4 2/5] hw/cxl/events: Update for rev3.2 common event record format Jonathan Cameron
@ 2026-01-19 11:15 ` Jonathan Cameron
2026-02-04 21:42 ` Ravi Jonnalagadda
2026-01-19 11:15 ` [PATCH qemu v4 4/5] hw/cxl/events: Updates for rev3.2 DRAM " Jonathan Cameron
` (2 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Jonathan Cameron @ 2026-01-19 11:15 UTC (permalink / raw)
To: Michael Tsirkin, qemu-devel, shiju.jose, armbru
Cc: linuxarm, linux-cxl, Ravi Shankar
From: Shiju Jose <shiju.jose@huawei.com>
CXL spec rev3.2 section 8.2.10.2.1.1 Table 8-57, general media event
table has updated with following new fields.
1. Advanced Programmable Corrected Memory Error Threshold Event Flags
2. Corrected Memory Error Count at Event
3. Memory Event Sub-Type
4. Support for component ID in the PLDM format.
Add updates for the above spec changes in the CXL general media event
reporting and QMP command to inject general media event.
In order to have one consistent source of references, update all to
references for this command to CXL r3.2.
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
v4: Update the spec reference in the related command to 3.2 as well.
(Markus)
v3: Update all references to 3.2 for consistency.
---
qapi/cxl.json | 29 +++++++++++++++++++++--------
include/hw/cxl/cxl_events.h | 7 +++++--
hw/mem/cxl_type3.c | 29 +++++++++++++++++++++++++++++
hw/mem/cxl_type3_stubs.c | 6 ++++++
4 files changed, 61 insertions(+), 10 deletions(-)
diff --git a/qapi/cxl.json b/qapi/cxl.json
index 82001c0591d8..4ff66fc6c16c 100644
--- a/qapi/cxl.json
+++ b/qapi/cxl.json
@@ -64,22 +64,22 @@
##
# @CXLGeneralMediaEvent:
#
-# Event record for a General Media Event (CXL r3.0 8.2.9.2.1.1).
+# Event record for a General Media Event (CXL r3.2 8.2.10.2.1.1).
#
# @dpa: Device Physical Address (relative to @path device). Note
-# lower bits include some flags. See CXL r3.0 Table 8-43 General
+# lower bits include some flags. See CXL r3.2 Table 8-57 General
# Media Event Record, Physical Address.
#
# @descriptor: Memory Event Descriptor with additional memory event
-# information. See CXL r3.0 Table 8-43 General Media Event
+# information. See CXL r3.2 Table 8-57 General Media Event
# Record, Memory Event Descriptor for bit definitions.
#
-# @type: Type of memory event that occurred. See CXL r3.0 Table 8-43
+# @type: Type of memory event that occurred. See CXL r3.2 Table 8-57
# General Media Event Record, Memory Event Type for possible
# values.
#
# @transaction-type: Type of first transaction that caused the event
-# to occur. See CXL r3.0 Table 8-43 General Media Event Record,
+# to occur. See CXL r3-2 Table 8-57 General Media Event Record,
# Transaction Type for possible values.
#
# @channel: The channel of the memory event location. A channel is an
@@ -94,6 +94,16 @@
# @component-id: Device specific component identifier for the event.
# May describe a field replaceable sub-component of the device.
#
+# @is-comp-id-pldm: This flag specifies whether the device-specific
+# component identifier format follows PLDM.
+#
+# @cme-ev-flags: Advanced programmable corrected memory error
+# threshold event flags.
+#
+# @cme-count: Corrected memory error count at event.
+#
+# @sub-type: Memory event sub-type.
+#
# Since: 8.1
##
{ 'struct': 'CXLGeneralMediaEvent',
@@ -101,13 +111,16 @@
'data': { 'dpa': 'uint64', 'descriptor': 'uint8',
'type': 'uint8', 'transaction-type': 'uint8',
'*channel': 'uint8', '*rank': 'uint8',
- '*device': 'uint32', '*component-id': 'str' } }
+ '*device': 'uint32', '*component-id': 'str',
+ '*is-comp-id-pldm':'bool',
+ '*cme-ev-flags':'uint8', '*cme-count':'uint32',
+ 'sub-type':'uint8' } }
##
# @cxl-inject-general-media-event:
#
-# Inject an event record for a General Media Event (CXL r3.0
-# 8.2.9.2.1.1). This event type is reported via one of the event
+# Inject an event record for a General Media Event (CXL r3.2
+# 8.2.10.2.1.1). This event type is reported via one of the event
# logs specified via the log parameter.
#
# Since: 8.1
diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h
index 4d9cfdb621ea..352f9891bd36 100644
--- a/include/hw/cxl/cxl_events.h
+++ b/include/hw/cxl/cxl_events.h
@@ -115,10 +115,10 @@ typedef struct CXLEventInterruptPolicy {
/*
* General Media Event Record
- * CXL r3.1 Section 8.2.9.2.1.1; Table 8-45
+ * CXL r3.2 Section 8.2.10.2.1.1; Table 8-57
*/
#define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10
-#define CXL_EVENT_GEN_MED_RES_SIZE 0x2e
+#define CXL_EVENT_GEN_MED_RES_SIZE 0x29
typedef struct CXLEventGenMedia {
CXLEventRecordHdr hdr;
uint64_t phys_addr;
@@ -130,6 +130,9 @@ typedef struct CXLEventGenMedia {
uint8_t rank;
uint8_t device[3];
uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
+ uint8_t cme_ev_flags;
+ uint8_t cme_count[3];
+ uint8_t sub_type;
uint8_t reserved[CXL_EVENT_GEN_MED_RES_SIZE];
} QEMU_PACKED CXLEventGenMedia;
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 371bd4dc6ab2..d03a9f0edc29 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -1646,6 +1646,11 @@ static const QemuUUID memory_module_uuid = {
#define CXL_GMER_VALID_RANK BIT(1)
#define CXL_GMER_VALID_DEVICE BIT(2)
#define CXL_GMER_VALID_COMPONENT BIT(3)
+#define CXL_GMER_VALID_COMPONENT_ID_FORMAT BIT(4)
+
+#define CXL_GMER_EV_DESC_UCE BIT(0)
+#define CXL_GMER_EV_DESC_THRESHOLD_EVENT BIT(1)
+#define CXL_GMER_EV_DESC_POISON_LIST_OVERFLOW_EVENT BIT(2)
static int ct3d_qmp_cxl_event_log_enc(CxlEventLog log)
{
@@ -1677,6 +1682,12 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
bool has_rank, uint8_t rank,
bool has_device, uint32_t device,
const char *component_id,
+ bool has_comp_id_pldm,
+ bool is_comp_id_pldm,
+ bool has_cme_ev_flags,
+ uint8_t cme_ev_flags,
+ bool has_cme_count, uint32_t cme_count,
+ uint8_t sub_type,
Error **errp)
{
Object *obj = object_resolve_path(path, NULL);
@@ -1737,10 +1748,28 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
strncpy((char *)gem.component_id, component_id,
sizeof(gem.component_id) - 1);
valid_flags |= CXL_GMER_VALID_COMPONENT;
+ if (has_comp_id_pldm && is_comp_id_pldm) {
+ valid_flags |= CXL_GMER_VALID_COMPONENT_ID_FORMAT;
+ }
}
stw_le_p(&gem.validity_flags, valid_flags);
+ if (has_cme_ev_flags) {
+ gem.cme_ev_flags = cme_ev_flags;
+ } else {
+ gem.cme_ev_flags = 0;
+ }
+
+ if (has_cme_count) {
+ descriptor |= CXL_GMER_EV_DESC_THRESHOLD_EVENT;
+ st24_le_p(gem.cme_count, cme_count);
+ } else {
+ st24_le_p(gem.cme_count, 0);
+ }
+
+ gem.sub_type = sub_type;
+
if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&gem)) {
cxl_event_irq_assert(ct3d);
}
diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c
index 91b1478114d9..2047e9784694 100644
--- a/hw/mem/cxl_type3_stubs.c
+++ b/hw/mem/cxl_type3_stubs.c
@@ -27,6 +27,12 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
bool has_rank, uint8_t rank,
bool has_device, uint32_t device,
const char *component_id,
+ bool has_comp_id_pldm,
+ bool is_comp_id_pldm,
+ bool has_cme_ev_flags,
+ uint8_t cme_ev_flags,
+ bool has_cme_count, uint32_t cme_count,
+ uint8_t sub_type,
Error **errp) {}
void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
--
2.48.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH qemu v4 4/5] hw/cxl/events: Updates for rev3.2 DRAM event record
2026-01-19 11:15 [PATCH qemu v4 0/5] cxl: r3.2 specification event updates Jonathan Cameron
` (2 preceding siblings ...)
2026-01-19 11:15 ` [PATCH qemu v4 3/5] hw/cxl/events: Updates for rev3.2 general media event record Jonathan Cameron
@ 2026-01-19 11:15 ` Jonathan Cameron
2026-02-04 21:44 ` Ravi Jonnalagadda
2026-01-19 11:15 ` [PATCH qemu v4 5/5] hw/cxl/events: Updates for rev3.2 memory module " Jonathan Cameron
2026-01-19 12:15 ` [PATCH qemu v4 0/5] cxl: r3.2 specification event updates Markus Armbruster
5 siblings, 1 reply; 13+ messages in thread
From: Jonathan Cameron @ 2026-01-19 11:15 UTC (permalink / raw)
To: Michael Tsirkin, qemu-devel, shiju.jose, armbru
Cc: linuxarm, linux-cxl, Ravi Shankar
From: Shiju Jose <shiju.jose@huawei.com>
CXL spec rev3.2 section 8.2.10.2.1.2 Table 8-58, DRAM event record
has updated with following new fields.
1. Component Identifier
2. Sub-channel of the memory event location
3. Advanced Programmable Corrected Memory Error Threshold Event Flags
4. Corrected Volatile Memory Error Count at Event
5. Memory Event Sub-Type
Add updates for the above spec changes in the CXL DRAM event
reporting and QMP command to inject DRAM event.
In order to ensure consistency update all specification references
for this command to CXL r3.2.
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
v4: Update spec reference in related command as well (Markus)
v3: Update all spec references for this command to 3.2 for consistency
(Markus)
---
qapi/cxl.json | 33 ++++++++++++++++++++++-------
include/hw/cxl/cxl_events.h | 9 ++++++--
hw/mem/cxl_type3.c | 42 +++++++++++++++++++++++++++++++++++++
hw/mem/cxl_type3_stubs.c | 7 +++++++
4 files changed, 82 insertions(+), 9 deletions(-)
diff --git a/qapi/cxl.json b/qapi/cxl.json
index 4ff66fc6c16c..1dc8b08ca301 100644
--- a/qapi/cxl.json
+++ b/qapi/cxl.json
@@ -131,21 +131,21 @@
##
# @CXLDRAMEvent:
#
-# Event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
+# Event record for a DRAM Event (CXL r3.2 8.2.10.2.1.2).
#
# @dpa: Device Physical Address (relative to @path device). Note
-# lower bits include some flags. See CXL r3.0 Table 8-44 DRAM
+# lower bits include some flags. See CXL r3.2 Table 8-58 DRAM
# Event Record, Physical Address.
#
# @descriptor: Memory Event Descriptor with additional memory event
-# information. See CXL r3.0 Table 8-44 DRAM Event Record, Memory
+# information. See CXL r3.2 Table 8-58 DRAM Event Record, Memory
# Event Descriptor for bit definitions.
#
-# @type: Type of memory event that occurred. See CXL r3.0 Table 8-44
+# @type: Type of memory event that occurred. See CXL r3.2 Table 8-58
# DRAM Event Record, Memory Event Type for possible values.
#
# @transaction-type: Type of first transaction that caused the event
-# to occur. See CXL r3.0 Table 8-44 DRAM Event Record,
+# to occur. See CXL r3.2 Table 8-58 DRAM Event Record,
# Transaction Type for possible values.
#
# @channel: The channel of the memory event location. A channel is an
@@ -169,6 +169,21 @@
# @correction-mask: Bits within each nibble. Used in order of bits
# set in the nibble-mask. Up to 4 nibbles may be covered.
#
+# @component-id: Device specific component identifier for the event.
+# May describe a field replaceable sub-component of the device.
+#
+# @is-comp-id-pldm: This flag specifies whether the device-specific
+# component identifier format follows PLDM.
+#
+# @sub-channel: The sub-channel of the memory event location.
+#
+# @cme-ev-flags: Advanced programmable corrected memory error
+# threshold event flags.
+#
+# @cvme-count: Corrected volatile memory error count at event.
+#
+# @sub-type: Memory event sub-type.
+#
# Since: 8.1
##
{ 'struct': 'CXLDRAMEvent',
@@ -177,13 +192,17 @@
'type': 'uint8', 'transaction-type': 'uint8',
'*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32',
'*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32',
- '*column': 'uint16', '*correction-mask': [ 'uint64' ]
+ '*column': 'uint16', '*correction-mask': [ 'uint64' ],
+ '*component-id': 'str', '*is-comp-id-pldm':'bool',
+ '*sub-channel':'uint8',
+ '*cme-ev-flags':'uint8', '*cvme-count':'uint32',
+ 'sub-type':'uint8'
}}
##
# @cxl-inject-dram-event:
#
-# Inject an event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
+# Inject an event record for a DRAM Event (CXL r3.2 8.2.10.2.1.2).
# This event type is reported via one of the event logs
# specified via the log parameter.
#
diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h
index 352f9891bd36..a3c5f2ec20e6 100644
--- a/include/hw/cxl/cxl_events.h
+++ b/include/hw/cxl/cxl_events.h
@@ -138,7 +138,7 @@ typedef struct CXLEventGenMedia {
/*
* DRAM Event Record
- * CXL r3.1 Section 8.2.9.2.1.2: Table 8-46
+ * CXL r3.2 Section 8.2.10.2.1.2: Table 8-58
* All fields little endian.
*/
typedef struct CXLEventDram {
@@ -156,7 +156,12 @@ typedef struct CXLEventDram {
uint8_t row[3];
uint16_t column;
uint64_t correction_mask[4];
- uint8_t reserved[0x17];
+ uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
+ uint8_t sub_channel;
+ uint8_t cme_ev_flags;
+ uint8_t cvme_count[3];
+ uint8_t sub_type;
+ uint8_t reserved;
} QEMU_PACKED CXLEventDram;
/*
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index d03a9f0edc29..3da538bafb64 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -1783,6 +1783,13 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
#define CXL_DRAM_VALID_ROW BIT(5)
#define CXL_DRAM_VALID_COLUMN BIT(6)
#define CXL_DRAM_VALID_CORRECTION_MASK BIT(7)
+#define CXL_DRAM_VALID_COMPONENT BIT(8)
+#define CXL_DRAM_VALID_COMPONENT_ID_FORMAT BIT(9)
+#define CXL_DRAM_VALID_SUB_CHANNEL BIT(10)
+
+#define CXL_DRAM_EV_DESC_UCE BIT(0)
+#define CXL_DRAM_EV_DESC_THRESHOLD_EVENT BIT(1)
+#define CXL_DRAM_EV_DESC_POISON_LIST_OVERFLOW_EVENT BIT(2)
void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
uint32_t flags,
@@ -1802,6 +1809,12 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
bool has_column, uint16_t column,
bool has_correction_mask,
uint64List *correction_mask,
+ const char *component_id,
+ bool has_comp_id_pldm, bool is_comp_id_pldm,
+ bool has_sub_channel, uint8_t sub_channel,
+ bool has_cme_ev_flags, uint8_t cme_ev_flags,
+ bool has_cvme_count, uint32_t cvme_count,
+ uint8_t sub_type,
Error **errp)
{
Object *obj = object_resolve_path(path, NULL);
@@ -1888,6 +1901,35 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
valid_flags |= CXL_DRAM_VALID_CORRECTION_MASK;
}
+ if (component_id) {
+ strncpy((char *)dram.component_id, component_id,
+ sizeof(dram.component_id) - 1);
+ valid_flags |= CXL_DRAM_VALID_COMPONENT;
+ if (has_comp_id_pldm && is_comp_id_pldm) {
+ valid_flags |= CXL_DRAM_VALID_COMPONENT_ID_FORMAT;
+ }
+ }
+
+ if (has_sub_channel) {
+ dram.sub_channel = sub_channel;
+ valid_flags |= CXL_DRAM_VALID_SUB_CHANNEL;
+ }
+
+ if (has_cme_ev_flags) {
+ dram.cme_ev_flags = cme_ev_flags;
+ } else {
+ dram.cme_ev_flags = 0;
+ }
+
+ if (has_cvme_count) {
+ descriptor |= CXL_DRAM_EV_DESC_THRESHOLD_EVENT;
+ st24_le_p(dram.cvme_count, cvme_count);
+ } else {
+ st24_le_p(dram.cvme_count, 0);
+ }
+
+ dram.sub_type = sub_type;
+
stw_le_p(&dram.validity_flags, valid_flags);
if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&dram)) {
diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c
index 2047e9784694..231dda263fa4 100644
--- a/hw/mem/cxl_type3_stubs.c
+++ b/hw/mem/cxl_type3_stubs.c
@@ -53,6 +53,13 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
bool has_column, uint16_t column,
bool has_correction_mask,
uint64List *correction_mask,
+ const char *component_id,
+ bool has_comp_id_pldm,
+ bool is_comp_id_pldm,
+ bool has_sub_channel, uint8_t sub_channel,
+ bool has_cme_ev_flags, uint8_t cme_ev_flags,
+ bool has_cvme_count, uint32_t cvme_count,
+ uint8_t sub_type,
Error **errp) {}
void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
--
2.48.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH qemu v4 5/5] hw/cxl/events: Updates for rev3.2 memory module event record
2026-01-19 11:15 [PATCH qemu v4 0/5] cxl: r3.2 specification event updates Jonathan Cameron
` (3 preceding siblings ...)
2026-01-19 11:15 ` [PATCH qemu v4 4/5] hw/cxl/events: Updates for rev3.2 DRAM " Jonathan Cameron
@ 2026-01-19 11:15 ` Jonathan Cameron
2026-02-04 21:46 ` Ravi Jonnalagadda
2026-01-19 12:15 ` [PATCH qemu v4 0/5] cxl: r3.2 specification event updates Markus Armbruster
5 siblings, 1 reply; 13+ messages in thread
From: Jonathan Cameron @ 2026-01-19 11:15 UTC (permalink / raw)
To: Michael Tsirkin, qemu-devel, shiju.jose, armbru
Cc: linuxarm, linux-cxl, Ravi Shankar
From: Shiju Jose <shiju.jose@huawei.com>
CXL spec rev3.2 section 8.2.10.2.1.3 Table 8-50, memory module
event record has updated with following new fields.
1. Validity Flags
2. Component Identifier
3. Device Event Sub-Type
Add updates for the above spec changes in the CXL memory module
event reporting and QMP command to inject memory module event.
Updated all references for this command to the CXL r3.2
specification.
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
v4: Update spec reference in the actual command as well (Markus)
V3: Update spec references for whole command (Markus)
---
qapi/cxl.json | 30 ++++++++++++++++++++----------
include/hw/cxl/cxl_events.h | 7 +++++--
hw/mem/cxl_type3.c | 20 ++++++++++++++++++++
hw/mem/cxl_type3_stubs.c | 4 ++++
4 files changed, 49 insertions(+), 12 deletions(-)
diff --git a/qapi/cxl.json b/qapi/cxl.json
index 1dc8b08ca301..81d6198ba030 100644
--- a/qapi/cxl.json
+++ b/qapi/cxl.json
@@ -214,20 +214,20 @@
##
# @CXLMemModuleEvent:
#
-# Event record for a Memory Module Event (CXL r3.0 8.2.9.2.1.3).
+# Event record for a Memory Module Event (CXL r3.2 8.2.10.2.1.3).
#
-# @type: Device Event Type. See CXL r3.0 Table 8-45 Memory Module
+# @type: Device Event Type. See CXL r3.2 Table 8-59 Memory Module
# Event Record for bit definitions for bit definiions.
#
-# @health-status: Overall health summary bitmap. See CXL r3.0 Table
-# 8-100 Get Health Info Output Payload, Health Status for bit
+# @health-status: Overall health summary bitmap. See CXL r3.2 Table
+# 8-148 Get Health Info Output Payload, Health Status for bit
# definitions.
#
-# @media-status: Overall media health summary. See CXL r3.0 Table
-# 8-100 Get Health Info Output Payload, Media Status for bit
+# @media-status: Overall media health summary. See CXL r3.2 Table
+# 8-148 Get Health Info Output Payload, Media Status for bit
# definitions.
#
-# @additional-status: See CXL r3.0 Table 8-100 Get Health Info Output
+# @additional-status: See CXL r3.2 Table 8-148 Get Health Info Output
# Payload, Additional Status for subfield definitions.
#
# @life-used: Percentage (0-100) of factory expected life span.
@@ -243,6 +243,14 @@
# @corrected-persistent-error-count: Total number of correctable
# errors in persistent memory
#
+# @component-id: Device specific component identifier for the event.
+# May describe a field replaceable sub-component of the device.
+#
+# @is-comp-id-pldm: This flag specifies whether the device-specific
+# component identifier format follows PLDM.
+#
+# @sub-type: Device event sub-type.
+#
# Since: 8.1
##
{ 'struct': 'CXLMemModuleEvent',
@@ -252,14 +260,16 @@
'life-used': 'uint8', 'temperature' : 'int16',
'dirty-shutdown-count': 'uint32',
'corrected-volatile-error-count': 'uint32',
- 'corrected-persistent-error-count': 'uint32'
+ 'corrected-persistent-error-count': 'uint32',
+ '*component-id': 'str', '*is-comp-id-pldm':'bool',
+ 'sub-type':'uint8'
}}
##
# @cxl-inject-memory-module-event:
#
-# Inject an event record for a Memory Module Event (CXL r3.0
-# 8.2.9.2.1.3). This event includes a copy of the Device Health info
+# Inject an event record for a Memory Module Event (CXL r3.2
+# 8.2.10.2.1.3). This event includes a copy of the Device Health info
# at the time of the event.
#
# Since: 8.1
diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h
index a3c5f2ec20e6..4a7836ad7227 100644
--- a/include/hw/cxl/cxl_events.h
+++ b/include/hw/cxl/cxl_events.h
@@ -166,7 +166,7 @@ typedef struct CXLEventDram {
/*
* Memory Module Event Record
- * CXL r3.1 Section 8.2.9.2.1.3: Table 8-47
+ * CXL r3.2 Section 8.2.10.2.1.3: Table 8-59
* All fields little endian.
*/
typedef struct CXLEventMemoryModule {
@@ -180,7 +180,10 @@ typedef struct CXLEventMemoryModule {
uint32_t dirty_shutdown_count;
uint32_t corrected_volatile_error_count;
uint32_t corrected_persistent_error_count;
- uint8_t reserved[0x3d];
+ uint16_t validity_flags;
+ uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
+ uint8_t sub_type;
+ uint8_t reserved[0x2a];
} QEMU_PACKED CXLEventMemoryModule;
/*
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 3da538bafb64..4dc9b223f476 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -1937,6 +1937,9 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
}
}
+#define CXL_MMER_VALID_COMPONENT BIT(0)
+#define CXL_MMER_VALID_COMPONENT_ID_FORMAT BIT(1)
+
void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
uint32_t flags, bool has_maint_op_class,
uint8_t maint_op_class,
@@ -1953,11 +1956,16 @@ void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
uint32_t dirty_shutdown_count,
uint32_t corrected_volatile_error_count,
uint32_t corrected_persist_error_count,
+ const char *component_id,
+ bool has_comp_id_pldm,
+ bool is_comp_id_pldm,
+ uint8_t sub_type,
Error **errp)
{
Object *obj = object_resolve_path(path, NULL);
CXLEventMemoryModule module;
CXLEventRecordHdr *hdr = &module.hdr;
+ uint16_t valid_flags = 0;
CXLDeviceState *cxlds;
CXLType3Dev *ct3d;
uint8_t enc_log;
@@ -2000,6 +2008,18 @@ void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
stl_le_p(&module.corrected_persistent_error_count,
corrected_persist_error_count);
+ if (component_id) {
+ strncpy((char *)module.component_id, component_id,
+ sizeof(module.component_id) - 1);
+ valid_flags |= CXL_MMER_VALID_COMPONENT;
+ if (has_comp_id_pldm && is_comp_id_pldm) {
+ valid_flags |= CXL_MMER_VALID_COMPONENT_ID_FORMAT;
+ }
+ }
+ module.sub_type = sub_type;
+
+ stw_le_p(&module.validity_flags, valid_flags);
+
if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&module)) {
cxl_event_irq_assert(ct3d);
}
diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c
index 231dda263fa4..98292a931c16 100644
--- a/hw/mem/cxl_type3_stubs.c
+++ b/hw/mem/cxl_type3_stubs.c
@@ -78,6 +78,10 @@ void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
uint32_t dirty_shutdown_count,
uint32_t corrected_volatile_error_count,
uint32_t corrected_persist_error_count,
+ const char *component_id,
+ bool has_comp_id_pldm,
+ bool is_comp_id_pldm,
+ uint8_t sub_type,
Error **errp) {}
void qmp_cxl_inject_poison(const char *path, uint64_t start, uint64_t length,
--
2.48.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH qemu v4 0/5] cxl: r3.2 specification event updates.
2026-01-19 11:15 [PATCH qemu v4 0/5] cxl: r3.2 specification event updates Jonathan Cameron
` (4 preceding siblings ...)
2026-01-19 11:15 ` [PATCH qemu v4 5/5] hw/cxl/events: Updates for rev3.2 memory module " Jonathan Cameron
@ 2026-01-19 12:15 ` Markus Armbruster
5 siblings, 0 replies; 13+ messages in thread
From: Markus Armbruster @ 2026-01-19 12:15 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Michael Tsirkin, qemu-devel, shiju.jose, armbru, linuxarm,
linux-cxl, Ravi Shankar
Series
Acked-by: Markus Armbruster <armbru@redhat.com>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH qemu v4 1/5] qapi: cxl: Refactor CXL event injection for common commands arguments
2026-01-19 11:15 ` [PATCH qemu v4 1/5] qapi: cxl: Refactor CXL event injection for common commands arguments Jonathan Cameron
@ 2026-02-04 21:34 ` Ravi Jonnalagadda
0 siblings, 0 replies; 13+ messages in thread
From: Ravi Jonnalagadda @ 2026-02-04 21:34 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Michael Tsirkin, qemu-devel, shiju.jose, armbru, linuxarm,
linux-cxl, Ravi Shankar
On Mon, Jan 19, 2026 at 3:21 AM Jonathan Cameron
<Jonathan.Cameron@huawei.com> wrote:
>
> From: Shiju Jose <shiju.jose@huawei.com>
>
> Refactor CXL event injection to use struct for common command
> arguments.
>
> Suggested-by: Markus Armbruster <armbru@redhat.com>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> ---
> v3: Fix wrong comment for memory module event (Markus)
> ---
> qapi/cxl.json | 89 +++++++++++++++++++++++++++++++++------------------
> 1 file changed, 58 insertions(+), 31 deletions(-)
>
> diff --git a/qapi/cxl.json b/qapi/cxl.json
> index eeddb58d1d3f..55a088586e53 100644
> --- a/qapi/cxl.json
> +++ b/qapi/cxl.json
> @@ -31,11 +31,10 @@
> }
>
> ##
> -# @cxl-inject-general-media-event:
> +# @CXLCommonEventBase:
> #
> -# Inject an event record for a General Media Event (CXL r3.0
> -# 8.2.9.2.1.1). This event type is reported via one of the event logs
> -# specified via the log parameter.
> +# Common event base for a CXL Event (CXL r3.0 8.2.9.2.1
> +# Table 8-42 Common Event Record Format).
> #
> # @path: CXL type 3 device canonical QOM path
> #
> @@ -44,6 +43,16 @@
> # @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
> # Record Format, Event Record Flags for subfield definitions.
> #
> +# Since: 8.1
> +##
> +{ 'struct': 'CXLCommonEventBase',
> + 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8' } }
> +
> +##
> +# @CXLGeneralMediaEvent:
> +#
> +# Event record for a General Media Event (CXL r3.0 8.2.9.2.1.1).
> +#
> # @dpa: Device Physical Address (relative to @path device). Note
> # lower bits include some flags. See CXL r3.0 Table 8-43 General
> # Media Event Record, Physical Address.
> @@ -74,26 +83,29 @@
> #
> # Since: 8.1
> ##
> -{ 'command': 'cxl-inject-general-media-event',
> - 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8',
> - 'dpa': 'uint64', 'descriptor': 'uint8',
> +{ 'struct': 'CXLGeneralMediaEvent',
> + 'base': 'CXLCommonEventBase',
> + 'data': { 'dpa': 'uint64', 'descriptor': 'uint8',
> 'type': 'uint8', 'transaction-type': 'uint8',
> '*channel': 'uint8', '*rank': 'uint8',
> '*device': 'uint32', '*component-id': 'str' } }
>
> ##
> -# @cxl-inject-dram-event:
> -#
> -# Inject an event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
> -# This event type is reported via one of the event logs specified via
> -# the log parameter.
> +# @cxl-inject-general-media-event:
> #
> -# @path: CXL type 3 device canonical QOM path
> +# Inject an event record for a General Media Event (CXL r3.0
> +# 8.2.9.2.1.1). This event type is reported via one of the event
> +# logs specified via the log parameter.
> #
> -# @log: Event log to add the event to
> +# Since: 8.1
> +##
> +{ 'command': 'cxl-inject-general-media-event',
> + 'data': 'CXLGeneralMediaEvent' }
> +
> +##
> +# @CXLDRAMEvent:
> #
> -# @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
> -# Record Format, Event Record Flags for subfield definitions.
> +# Event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
> #
> # @dpa: Device Physical Address (relative to @path device). Note
> # lower bits include some flags. See CXL r3.0 Table 8-44 DRAM
> @@ -133,9 +145,9 @@
> #
> # Since: 8.1
> ##
> -{ 'command': 'cxl-inject-dram-event',
> - 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8',
> - 'dpa': 'uint64', 'descriptor': 'uint8',
> +{ 'struct': 'CXLDRAMEvent',
> + 'base': 'CXLCommonEventBase',
> + 'data': { 'dpa': 'uint64', 'descriptor': 'uint8',
> 'type': 'uint8', 'transaction-type': 'uint8',
> '*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32',
> '*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32',
> @@ -143,18 +155,21 @@
> }}
>
> ##
> -# @cxl-inject-memory-module-event:
> -#
> -# Inject an event record for a Memory Module Event (CXL r3.0
> -# 8.2.9.2.1.3). This event includes a copy of the Device Health info
> -# at the time of the event.
> +# @cxl-inject-dram-event:
> #
> -# @path: CXL type 3 device canonical QOM path
> +# Inject an event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
> +# This event type is reported via one of the event logs
> +# specified via the log parameter.
> #
> -# @log: Event Log to add the event to
> +# Since: 8.1
> +##
> +{ 'command': 'cxl-inject-dram-event',
> + 'data': 'CXLDRAMEvent' }
> +
> +##
> +# @CXLMemModuleEvent:
> #
> -# @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
> -# Record Format, Event Record Flags for subfield definitions.
> +# Event record for a Memory Module Event (CXL r3.0 8.2.9.2.1.3).
> #
> # @type: Device Event Type. See CXL r3.0 Table 8-45 Memory Module
> # Event Record for bit definitions for bit definiions.
> @@ -185,9 +200,9 @@
> #
> # Since: 8.1
> ##
> -{ 'command': 'cxl-inject-memory-module-event',
> - 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags' : 'uint8',
> - 'type': 'uint8', 'health-status': 'uint8',
> +{ 'struct': 'CXLMemModuleEvent',
> + 'base': 'CXLCommonEventBase',
> + 'data': { 'type': 'uint8', 'health-status': 'uint8',
> 'media-status': 'uint8', 'additional-status': 'uint8',
> 'life-used': 'uint8', 'temperature' : 'int16',
> 'dirty-shutdown-count': 'uint32',
> @@ -195,6 +210,18 @@
> 'corrected-persistent-error-count': 'uint32'
> }}
>
> +##
> +# @cxl-inject-memory-module-event:
> +#
> +# Inject an event record for a Memory Module Event (CXL r3.0
> +# 8.2.9.2.1.3). This event includes a copy of the Device Health info
> +# at the time of the event.
> +#
> +# Since: 8.1
> +##
> +{ 'command': 'cxl-inject-memory-module-event',
> + 'data': 'CXLMemModuleEvent' }
> +
> ##
> # @cxl-inject-poison:
> #
> --
> 2.48.1
>
>
No comments.
Reviewed-by: Ravi Jonnalagadda <ravis.opensrc@gmail.com>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH qemu v4 2/5] hw/cxl/events: Update for rev3.2 common event record format
2026-01-19 11:15 ` [PATCH qemu v4 2/5] hw/cxl/events: Update for rev3.2 common event record format Jonathan Cameron
@ 2026-02-04 21:35 ` Ravi Jonnalagadda
0 siblings, 0 replies; 13+ messages in thread
From: Ravi Jonnalagadda @ 2026-02-04 21:35 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Michael Tsirkin, qemu-devel, shiju.jose, armbru, linuxarm,
linux-cxl, Ravi Shankar
On Mon, Jan 19, 2026 at 3:16 AM Jonathan Cameron
<Jonathan.Cameron@huawei.com> wrote:
>
> From: Shiju Jose <shiju.jose@huawei.com>
>
> CXL spec 3.2 section 8.2.9.2.1 Table 8-55, Common Event Record
> format has updated with optional Maintenance Operation Subclass,
> LD ID and ID of the device head information.
>
> Add updates for the above optional parameters in the related
> CXL events reporting and in the QMP commands to inject CXL events.
>
> Update all related specification references to CXL r3.2 to ensure
> one consistent source.
>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> v3: Expand the LD acronym (Markus)
> ---
> qapi/cxl.json | 21 ++++++++---
> include/hw/cxl/cxl_device.h | 7 +++-
> include/hw/cxl/cxl_events.h | 15 ++++++--
> hw/cxl/cxl-events.c | 3 +-
> hw/cxl/cxl-mailbox-utils.c | 3 +-
> hw/mem/cxl_type3.c | 70 ++++++++++++++++++++++++++++++++-----
> hw/mem/cxl_type3_stubs.c | 24 +++++++++++--
> 7 files changed, 122 insertions(+), 21 deletions(-)
>
> diff --git a/qapi/cxl.json b/qapi/cxl.json
> index 55a088586e53..82001c0591d8 100644
> --- a/qapi/cxl.json
> +++ b/qapi/cxl.json
> @@ -33,20 +33,33 @@
> ##
> # @CXLCommonEventBase:
> #
> -# Common event base for a CXL Event (CXL r3.0 8.2.9.2.1
> -# Table 8-42 Common Event Record Format).
> +# Common event base for a CXL Event (CXL r3.2 8.2.10.2.1
> +# Table 8-55 Common Event Record Format).
> #
> # @path: CXL type 3 device canonical QOM path
> #
> # @log: event log to add the event to
> #
> -# @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
> +# @flags: Event Record Flags. See CXL r3.2 Table 8-55 Common Event
> # Record Format, Event Record Flags for subfield definitions.
> #
> +# @maint-op-class: Maintenance operation class the device requests to
> +# initiate.
> +#
> +# @maint-op-subclass: Maintenance operation subclass the device
> +# requests to initiate.
> +#
> +# @ld-id: Logical Device (LD) ID of LD from where the event
> +# originated.
> +#
> +# @head-id: ID of the device head from where the event originated.
> +#
> # Since: 8.1
> ##
> { 'struct': 'CXLCommonEventBase',
> - 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8' } }
> + 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint32',
> + '*maint-op-class':'uint8', '*maint-op-subclass':'uint8',
> + '*ld-id':'uint16', '*head-id':'uint8' } }
>
> ##
> # @CXLGeneralMediaEvent:
> diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
> index 165355baf9da..e461a824b692 100644
> --- a/include/hw/cxl/cxl_device.h
> +++ b/include/hw/cxl/cxl_device.h
> @@ -723,7 +723,12 @@ bool ct3_test_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa,
> uint64_t len);
> void cxl_assign_event_header(CXLEventRecordHdr *hdr,
> const QemuUUID *uuid, uint32_t flags,
> - uint8_t length, uint64_t timestamp);
> + uint8_t length, uint64_t timestamp,
> + bool has_maint_op_class, uint8_t maint_op_class,
> + bool has_maint_op_subclass,
> + uint8_t maint_op_subclass,
> + bool has_ld_id, uint16_t ld_id,
> + bool has_head_id, uint8_t head_id);
> void cxl_create_dc_event_records_for_extents(CXLType3Dev *ct3d,
> CXLDCEventType type,
> CXLDCExtentRaw extents[],
> diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h
> index 758b075a64b9..4d9cfdb621ea 100644
> --- a/include/hw/cxl/cxl_events.h
> +++ b/include/hw/cxl/cxl_events.h
> @@ -29,9 +29,15 @@ typedef enum CXLEventLogType {
>
> /*
> * Common Event Record Format
> - * CXL r3.1 section 8.2.9.2.1: Event Records; Table 8-43
> + * CXL r3.2 section 8.2.10.2.1: Event Records; Table 8-55
> */
> -#define CXL_EVENT_REC_HDR_RES_LEN 0xf
> +#define CXL_EVENT_REC_FLAGS_PERMANENT_COND BIT(2)
> +#define CXL_EVENT_REC_FLAGS_MAINT_NEEDED BIT(3)
> +#define CXL_EVENT_REC_FLAGS_PERF_DEGRADED BIT(4)
> +#define CXL_EVENT_REC_FLAGS_HW_REPLACEMENT_NEEDED BIT(5)
> +#define CXL_EVENT_REC_FLAGS_MAINT_OP_SUBCLASS_VALID BIT(6)
> +#define CXL_EVENT_REC_FLAGS_LD_ID_VALID BIT(7)
> +#define CXL_EVENT_REC_FLAGS_HEAD_ID_VALID BIT(8)
> typedef struct CXLEventRecordHdr {
> QemuUUID id;
> uint8_t length;
> @@ -40,7 +46,10 @@ typedef struct CXLEventRecordHdr {
> uint16_t related_handle;
> uint64_t timestamp;
> uint8_t maint_op_class;
> - uint8_t reserved[CXL_EVENT_REC_HDR_RES_LEN];
> + uint8_t maint_op_subclass;
> + uint16_t ld_id;
> + uint8_t head_id;
> + uint8_t reserved[0xb];
> } QEMU_PACKED CXLEventRecordHdr;
>
> #define CXL_EVENT_RECORD_DATA_LENGTH 0x50
> diff --git a/hw/cxl/cxl-events.c b/hw/cxl/cxl-events.c
> index 7583dd9162f6..5356dfb5b300 100644
> --- a/hw/cxl/cxl-events.c
> +++ b/hw/cxl/cxl-events.c
> @@ -271,7 +271,8 @@ void cxl_create_dc_event_records_for_extents(CXLType3Dev *ct3d,
> &dynamic_capacity_uuid,
> (1 << CXL_EVENT_TYPE_INFO),
> sizeof(event_rec),
> - cxl_device_get_timestamp(&ct3d->cxl_dstate));
> + cxl_device_get_timestamp(&ct3d->cxl_dstate),
> + 0, 0, 0, 0, 0, 0, 0, 0);
> event_rec.type = type;
> event_rec.validity_flags = 1;
> event_rec.host_id = 0;
> diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
> index 6cfdd98168f9..e9528da70cc4 100644
> --- a/hw/cxl/cxl-mailbox-utils.c
> +++ b/hw/cxl/cxl-mailbox-utils.c
> @@ -3458,7 +3458,8 @@ static CXLRetCode cmd_fm_set_dc_region_config(const struct cxl_cmd *cmd,
> &dynamic_capacity_uuid,
> (1 << CXL_EVENT_TYPE_INFO),
> sizeof(dcEvent),
> - cxl_device_get_timestamp(&ct3d->cxl_dstate));
> + cxl_device_get_timestamp(&ct3d->cxl_dstate),
> + 0, 0, 0, 0, 0, 0, 0, 0);
> dcEvent.type = DC_EVENT_REGION_CONFIG_UPDATED;
> dcEvent.validity_flags = 1;
> dcEvent.host_id = 0;
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index 6eb20137a04f..371bd4dc6ab2 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -1592,12 +1592,39 @@ void qmp_cxl_inject_correctable_error(const char *path, CxlCorErrorType type,
>
> void cxl_assign_event_header(CXLEventRecordHdr *hdr,
> const QemuUUID *uuid, uint32_t flags,
> - uint8_t length, uint64_t timestamp)
> + uint8_t length, uint64_t timestamp,
> + bool has_maint_op_class, uint8_t maint_op_class,
> + bool has_maint_op_subclass,
> + uint8_t maint_op_subclass,
> + bool has_ld_id, uint16_t ld_id,
> + bool has_head_id, uint8_t head_id)
> {
> - st24_le_p(&hdr->flags, flags);
> hdr->length = length;
> memcpy(&hdr->id, uuid, sizeof(hdr->id));
> stq_le_p(&hdr->timestamp, timestamp);
> +
> + if (has_maint_op_class) {
> + hdr->maint_op_class = maint_op_class;
> + } else {
> + hdr->maint_op_class = 0;
> + }
> +
> + if (has_maint_op_subclass) {
> + flags |= CXL_EVENT_REC_FLAGS_MAINT_OP_SUBCLASS_VALID;
> + hdr->maint_op_subclass = maint_op_subclass;
> + }
> +
> + if (has_ld_id) {
> + flags |= CXL_EVENT_REC_FLAGS_LD_ID_VALID;
> + stw_le_p(&hdr->ld_id, ld_id);
> + }
> +
> + if (has_head_id) {
> + flags |= CXL_EVENT_REC_FLAGS_HEAD_ID_VALID;
> + hdr->head_id = head_id;
> + }
> +
> + st24_le_p(&hdr->flags, flags);
> }
>
> static const QemuUUID gen_media_uuid = {
> @@ -1637,7 +1664,13 @@ static int ct3d_qmp_cxl_event_log_enc(CxlEventLog log)
> }
> /* Component ID is device specific. Define this as a string. */
> void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
> - uint8_t flags, uint64_t dpa,
> + uint32_t flags, bool has_maint_op_class,
> + uint8_t maint_op_class,
> + bool has_maint_op_subclass,
> + uint8_t maint_op_subclass,
> + bool has_ld_id, uint16_t ld_id,
> + bool has_head_id, uint8_t head_id,
> + uint64_t dpa,
> uint8_t descriptor, uint8_t type,
> uint8_t transaction_type,
> bool has_channel, uint8_t channel,
> @@ -1675,7 +1708,10 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
>
> memset(&gem, 0, sizeof(gem));
> cxl_assign_event_header(hdr, &gen_media_uuid, flags, sizeof(gem),
> - cxl_device_get_timestamp(&ct3d->cxl_dstate));
> + cxl_device_get_timestamp(&ct3d->cxl_dstate),
> + has_maint_op_class, maint_op_class,
> + has_maint_op_subclass, maint_op_subclass,
> + has_ld_id, ld_id, has_head_id, head_id);
>
> stq_le_p(&gem.phys_addr, dpa);
> gem.descriptor = descriptor;
> @@ -1719,7 +1755,13 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
> #define CXL_DRAM_VALID_COLUMN BIT(6)
> #define CXL_DRAM_VALID_CORRECTION_MASK BIT(7)
>
> -void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
> +void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
> + uint32_t flags,
> + bool has_maint_op_class, uint8_t maint_op_class,
> + bool has_maint_op_subclass,
> + uint8_t maint_op_subclass,
> + bool has_ld_id, uint16_t ld_id,
> + bool has_head_id, uint8_t head_id,
> uint64_t dpa, uint8_t descriptor,
> uint8_t type, uint8_t transaction_type,
> bool has_channel, uint8_t channel,
> @@ -1762,7 +1804,10 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
>
> memset(&dram, 0, sizeof(dram));
> cxl_assign_event_header(hdr, &dram_uuid, flags, sizeof(dram),
> - cxl_device_get_timestamp(&ct3d->cxl_dstate));
> + cxl_device_get_timestamp(&ct3d->cxl_dstate),
> + has_maint_op_class, maint_op_class,
> + has_maint_op_subclass, maint_op_subclass,
> + has_ld_id, ld_id, has_head_id, head_id);
> stq_le_p(&dram.phys_addr, dpa);
> dram.descriptor = descriptor;
> dram.type = type;
> @@ -1822,7 +1867,13 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
> }
>
> void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
> - uint8_t flags, uint8_t type,
> + uint32_t flags, bool has_maint_op_class,
> + uint8_t maint_op_class,
> + bool has_maint_op_subclass,
> + uint8_t maint_op_subclass,
> + bool has_ld_id, uint16_t ld_id,
> + bool has_head_id, uint8_t head_id,
> + uint8_t type,
> uint8_t health_status,
> uint8_t media_status,
> uint8_t additional_status,
> @@ -1861,7 +1912,10 @@ void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
>
> memset(&module, 0, sizeof(module));
> cxl_assign_event_header(hdr, &memory_module_uuid, flags, sizeof(module),
> - cxl_device_get_timestamp(&ct3d->cxl_dstate));
> + cxl_device_get_timestamp(&ct3d->cxl_dstate),
> + has_maint_op_class, maint_op_class,
> + has_maint_op_subclass, maint_op_subclass,
> + has_ld_id, ld_id, has_head_id, head_id);
>
> module.type = type;
> module.health_status = health_status;
> diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c
> index c1a5e4a7c193..91b1478114d9 100644
> --- a/hw/mem/cxl_type3_stubs.c
> +++ b/hw/mem/cxl_type3_stubs.c
> @@ -14,7 +14,13 @@
> #include "qapi/qapi-commands-cxl.h"
>
> void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
> - uint8_t flags, uint64_t dpa,
> + uint32_t flags, bool has_maint_op_class,
> + uint8_t maint_op_class,
> + bool has_maint_op_subclass,
> + uint8_t maint_op_subclass,
> + bool has_ld_id, uint16_t ld_id,
> + bool has_head_id, uint8_t head_id,
> + uint64_t dpa,
> uint8_t descriptor, uint8_t type,
> uint8_t transaction_type,
> bool has_channel, uint8_t channel,
> @@ -23,7 +29,13 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
> const char *component_id,
> Error **errp) {}
>
> -void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
> +void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
> + uint32_t flags,
> + bool has_maint_op_class, uint8_t maint_op_class,
> + bool has_maint_op_subclass,
> + uint8_t maint_op_subclass,
> + bool has_ld_id, uint16_t ld_id,
> + bool has_head_id, uint8_t head_id,
> uint64_t dpa, uint8_t descriptor,
> uint8_t type, uint8_t transaction_type,
> bool has_channel, uint8_t channel,
> @@ -38,7 +50,13 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
> Error **errp) {}
>
> void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
> - uint8_t flags, uint8_t type,
> + uint32_t flags, bool has_maint_op_class,
> + uint8_t maint_op_class,
> + bool has_maint_op_subclass,
> + uint8_t maint_op_subclass,
> + bool has_ld_id, uint16_t ld_id,
> + bool has_head_id, uint8_t head_id,
> + uint8_t type,
> uint8_t health_status,
> uint8_t media_status,
> uint8_t additional_status,
> --
> 2.48.1
>
>
No comments.
Reviewed-by: Ravi Jonnalagadda <ravis.opensrc@gmail.com>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH qemu v4 3/5] hw/cxl/events: Updates for rev3.2 general media event record
2026-01-19 11:15 ` [PATCH qemu v4 3/5] hw/cxl/events: Updates for rev3.2 general media event record Jonathan Cameron
@ 2026-02-04 21:42 ` Ravi Jonnalagadda
2026-02-05 10:58 ` Shiju Jose
0 siblings, 1 reply; 13+ messages in thread
From: Ravi Jonnalagadda @ 2026-02-04 21:42 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Michael Tsirkin, qemu-devel, shiju.jose, armbru, linuxarm,
linux-cxl, Ravi Shankar
On Mon, Jan 19, 2026 at 3:21 AM Jonathan Cameron
<Jonathan.Cameron@huawei.com> wrote:
>
> From: Shiju Jose <shiju.jose@huawei.com>
>
> CXL spec rev3.2 section 8.2.10.2.1.1 Table 8-57, general media event
> table has updated with following new fields.
> 1. Advanced Programmable Corrected Memory Error Threshold Event Flags
> 2. Corrected Memory Error Count at Event
> 3. Memory Event Sub-Type
> 4. Support for component ID in the PLDM format.
>
> Add updates for the above spec changes in the CXL general media event
> reporting and QMP command to inject general media event.
>
> In order to have one consistent source of references, update all to
> references for this command to CXL r3.2.
>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> v4: Update the spec reference in the related command to 3.2 as well.
> (Markus)
> v3: Update all references to 3.2 for consistency.
> ---
> qapi/cxl.json | 29 +++++++++++++++++++++--------
> include/hw/cxl/cxl_events.h | 7 +++++--
> hw/mem/cxl_type3.c | 29 +++++++++++++++++++++++++++++
> hw/mem/cxl_type3_stubs.c | 6 ++++++
> 4 files changed, 61 insertions(+), 10 deletions(-)
>
> diff --git a/qapi/cxl.json b/qapi/cxl.json
> index 82001c0591d8..4ff66fc6c16c 100644
> --- a/qapi/cxl.json
> +++ b/qapi/cxl.json
> @@ -64,22 +64,22 @@
> ##
> # @CXLGeneralMediaEvent:
> #
> -# Event record for a General Media Event (CXL r3.0 8.2.9.2.1.1).
> +# Event record for a General Media Event (CXL r3.2 8.2.10.2.1.1).
> #
> # @dpa: Device Physical Address (relative to @path device). Note
> -# lower bits include some flags. See CXL r3.0 Table 8-43 General
> +# lower bits include some flags. See CXL r3.2 Table 8-57 General
> # Media Event Record, Physical Address.
> #
> # @descriptor: Memory Event Descriptor with additional memory event
> -# information. See CXL r3.0 Table 8-43 General Media Event
> +# information. See CXL r3.2 Table 8-57 General Media Event
> # Record, Memory Event Descriptor for bit definitions.
> #
> -# @type: Type of memory event that occurred. See CXL r3.0 Table 8-43
> +# @type: Type of memory event that occurred. See CXL r3.2 Table 8-57
> # General Media Event Record, Memory Event Type for possible
> # values.
> #
> # @transaction-type: Type of first transaction that caused the event
> -# to occur. See CXL r3.0 Table 8-43 General Media Event Record,
> +# to occur. See CXL r3-2 Table 8-57 General Media Event Record,
> # Transaction Type for possible values.
> #
> # @channel: The channel of the memory event location. A channel is an
> @@ -94,6 +94,16 @@
> # @component-id: Device specific component identifier for the event.
> # May describe a field replaceable sub-component of the device.
> #
> +# @is-comp-id-pldm: This flag specifies whether the device-specific
> +# component identifier format follows PLDM.
> +#
> +# @cme-ev-flags: Advanced programmable corrected memory error
> +# threshold event flags.
> +#
> +# @cme-count: Corrected memory error count at event.
> +#
> +# @sub-type: Memory event sub-type.
> +#
> # Since: 8.1
> ##
> { 'struct': 'CXLGeneralMediaEvent',
> @@ -101,13 +111,16 @@
> 'data': { 'dpa': 'uint64', 'descriptor': 'uint8',
> 'type': 'uint8', 'transaction-type': 'uint8',
> '*channel': 'uint8', '*rank': 'uint8',
> - '*device': 'uint32', '*component-id': 'str' } }
> + '*device': 'uint32', '*component-id': 'str',
> + '*is-comp-id-pldm':'bool',
> + '*cme-ev-flags':'uint8', '*cme-count':'uint32',
> + 'sub-type':'uint8' } }
>
> ##
> # @cxl-inject-general-media-event:
> #
> -# Inject an event record for a General Media Event (CXL r3.0
> -# 8.2.9.2.1.1). This event type is reported via one of the event
> +# Inject an event record for a General Media Event (CXL r3.2
> +# 8.2.10.2.1.1). This event type is reported via one of the event
> # logs specified via the log parameter.
> #
> # Since: 8.1
> diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h
> index 4d9cfdb621ea..352f9891bd36 100644
> --- a/include/hw/cxl/cxl_events.h
> +++ b/include/hw/cxl/cxl_events.h
> @@ -115,10 +115,10 @@ typedef struct CXLEventInterruptPolicy {
>
> /*
> * General Media Event Record
> - * CXL r3.1 Section 8.2.9.2.1.1; Table 8-45
> + * CXL r3.2 Section 8.2.10.2.1.1; Table 8-57
> */
> #define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10
> -#define CXL_EVENT_GEN_MED_RES_SIZE 0x2e
> +#define CXL_EVENT_GEN_MED_RES_SIZE 0x29
> typedef struct CXLEventGenMedia {
> CXLEventRecordHdr hdr;
> uint64_t phys_addr;
> @@ -130,6 +130,9 @@ typedef struct CXLEventGenMedia {
> uint8_t rank;
> uint8_t device[3];
> uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
> + uint8_t cme_ev_flags;
> + uint8_t cme_count[3];
> + uint8_t sub_type;
> uint8_t reserved[CXL_EVENT_GEN_MED_RES_SIZE];
> } QEMU_PACKED CXLEventGenMedia;
>
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index 371bd4dc6ab2..d03a9f0edc29 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -1646,6 +1646,11 @@ static const QemuUUID memory_module_uuid = {
> #define CXL_GMER_VALID_RANK BIT(1)
> #define CXL_GMER_VALID_DEVICE BIT(2)
> #define CXL_GMER_VALID_COMPONENT BIT(3)
> +#define CXL_GMER_VALID_COMPONENT_ID_FORMAT BIT(4)
> +
> +#define CXL_GMER_EV_DESC_UCE BIT(0)
> +#define CXL_GMER_EV_DESC_THRESHOLD_EVENT BIT(1)
> +#define CXL_GMER_EV_DESC_POISON_LIST_OVERFLOW_EVENT BIT(2)
>
> static int ct3d_qmp_cxl_event_log_enc(CxlEventLog log)
> {
> @@ -1677,6 +1682,12 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
> bool has_rank, uint8_t rank,
> bool has_device, uint32_t device,
> const char *component_id,
> + bool has_comp_id_pldm,
> + bool is_comp_id_pldm,
> + bool has_cme_ev_flags,
> + uint8_t cme_ev_flags,
> + bool has_cme_count, uint32_t cme_count,
> + uint8_t sub_type,
> Error **errp)
> {
> Object *obj = object_resolve_path(path, NULL);
> @@ -1737,10 +1748,28 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
> strncpy((char *)gem.component_id, component_id,
> sizeof(gem.component_id) - 1);
> valid_flags |= CXL_GMER_VALID_COMPONENT;
> + if (has_comp_id_pldm && is_comp_id_pldm) {
> + valid_flags |= CXL_GMER_VALID_COMPONENT_ID_FORMAT;
> + }
> }
>
> stw_le_p(&gem.validity_flags, valid_flags);
>
> + if (has_cme_ev_flags) {
> + gem.cme_ev_flags = cme_ev_flags;
> + } else {
> + gem.cme_ev_flags = 0;
> + }
> +
> + if (has_cme_count) {
> + descriptor |= CXL_GMER_EV_DESC_THRESHOLD_EVENT;
The modification to 'descriptor' here is not written back to gem.descriptor
which was assigned earlier in this function.
Suggest moving gem.descriptor assignment after this block, similar to
how valid_flags is handled in this same function.
> + st24_le_p(gem.cme_count, cme_count);
> + } else {
> + st24_le_p(gem.cme_count, 0);
> + }
> +
> + gem.sub_type = sub_type;
> +
> if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&gem)) {
> cxl_event_irq_assert(ct3d);
> }
> diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c
> index 91b1478114d9..2047e9784694 100644
> --- a/hw/mem/cxl_type3_stubs.c
> +++ b/hw/mem/cxl_type3_stubs.c
> @@ -27,6 +27,12 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
> bool has_rank, uint8_t rank,
> bool has_device, uint32_t device,
> const char *component_id,
> + bool has_comp_id_pldm,
> + bool is_comp_id_pldm,
> + bool has_cme_ev_flags,
> + uint8_t cme_ev_flags,
> + bool has_cme_count, uint32_t cme_count,
> + uint8_t sub_type,
> Error **errp) {}
>
> void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
> --
> 2.48.1
>
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH qemu v4 4/5] hw/cxl/events: Updates for rev3.2 DRAM event record
2026-01-19 11:15 ` [PATCH qemu v4 4/5] hw/cxl/events: Updates for rev3.2 DRAM " Jonathan Cameron
@ 2026-02-04 21:44 ` Ravi Jonnalagadda
0 siblings, 0 replies; 13+ messages in thread
From: Ravi Jonnalagadda @ 2026-02-04 21:44 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Michael Tsirkin, qemu-devel, shiju.jose, armbru, linuxarm,
linux-cxl, Ravi Shankar
On Mon, Jan 19, 2026 at 3:21 AM Jonathan Cameron
<Jonathan.Cameron@huawei.com> wrote:
>
> From: Shiju Jose <shiju.jose@huawei.com>
>
> CXL spec rev3.2 section 8.2.10.2.1.2 Table 8-58, DRAM event record
> has updated with following new fields.
> 1. Component Identifier
> 2. Sub-channel of the memory event location
> 3. Advanced Programmable Corrected Memory Error Threshold Event Flags
> 4. Corrected Volatile Memory Error Count at Event
> 5. Memory Event Sub-Type
>
> Add updates for the above spec changes in the CXL DRAM event
> reporting and QMP command to inject DRAM event.
>
> In order to ensure consistency update all specification references
> for this command to CXL r3.2.
>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> v4: Update spec reference in related command as well (Markus)
> v3: Update all spec references for this command to 3.2 for consistency
> (Markus)
> ---
> qapi/cxl.json | 33 ++++++++++++++++++++++-------
> include/hw/cxl/cxl_events.h | 9 ++++++--
> hw/mem/cxl_type3.c | 42 +++++++++++++++++++++++++++++++++++++
> hw/mem/cxl_type3_stubs.c | 7 +++++++
> 4 files changed, 82 insertions(+), 9 deletions(-)
>
> diff --git a/qapi/cxl.json b/qapi/cxl.json
> index 4ff66fc6c16c..1dc8b08ca301 100644
> --- a/qapi/cxl.json
> +++ b/qapi/cxl.json
> @@ -131,21 +131,21 @@
> ##
> # @CXLDRAMEvent:
> #
> -# Event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
> +# Event record for a DRAM Event (CXL r3.2 8.2.10.2.1.2).
> #
> # @dpa: Device Physical Address (relative to @path device). Note
> -# lower bits include some flags. See CXL r3.0 Table 8-44 DRAM
> +# lower bits include some flags. See CXL r3.2 Table 8-58 DRAM
> # Event Record, Physical Address.
> #
> # @descriptor: Memory Event Descriptor with additional memory event
> -# information. See CXL r3.0 Table 8-44 DRAM Event Record, Memory
> +# information. See CXL r3.2 Table 8-58 DRAM Event Record, Memory
> # Event Descriptor for bit definitions.
> #
> -# @type: Type of memory event that occurred. See CXL r3.0 Table 8-44
> +# @type: Type of memory event that occurred. See CXL r3.2 Table 8-58
> # DRAM Event Record, Memory Event Type for possible values.
> #
> # @transaction-type: Type of first transaction that caused the event
> -# to occur. See CXL r3.0 Table 8-44 DRAM Event Record,
> +# to occur. See CXL r3.2 Table 8-58 DRAM Event Record,
> # Transaction Type for possible values.
> #
> # @channel: The channel of the memory event location. A channel is an
> @@ -169,6 +169,21 @@
> # @correction-mask: Bits within each nibble. Used in order of bits
> # set in the nibble-mask. Up to 4 nibbles may be covered.
> #
> +# @component-id: Device specific component identifier for the event.
> +# May describe a field replaceable sub-component of the device.
> +#
> +# @is-comp-id-pldm: This flag specifies whether the device-specific
> +# component identifier format follows PLDM.
> +#
> +# @sub-channel: The sub-channel of the memory event location.
> +#
> +# @cme-ev-flags: Advanced programmable corrected memory error
> +# threshold event flags.
> +#
> +# @cvme-count: Corrected volatile memory error count at event.
> +#
> +# @sub-type: Memory event sub-type.
> +#
> # Since: 8.1
> ##
> { 'struct': 'CXLDRAMEvent',
> @@ -177,13 +192,17 @@
> 'type': 'uint8', 'transaction-type': 'uint8',
> '*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32',
> '*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32',
> - '*column': 'uint16', '*correction-mask': [ 'uint64' ]
> + '*column': 'uint16', '*correction-mask': [ 'uint64' ],
> + '*component-id': 'str', '*is-comp-id-pldm':'bool',
> + '*sub-channel':'uint8',
> + '*cme-ev-flags':'uint8', '*cvme-count':'uint32',
> + 'sub-type':'uint8'
> }}
>
> ##
> # @cxl-inject-dram-event:
> #
> -# Inject an event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
> +# Inject an event record for a DRAM Event (CXL r3.2 8.2.10.2.1.2).
> # This event type is reported via one of the event logs
> # specified via the log parameter.
> #
> diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h
> index 352f9891bd36..a3c5f2ec20e6 100644
> --- a/include/hw/cxl/cxl_events.h
> +++ b/include/hw/cxl/cxl_events.h
> @@ -138,7 +138,7 @@ typedef struct CXLEventGenMedia {
>
> /*
> * DRAM Event Record
> - * CXL r3.1 Section 8.2.9.2.1.2: Table 8-46
> + * CXL r3.2 Section 8.2.10.2.1.2: Table 8-58
> * All fields little endian.
> */
> typedef struct CXLEventDram {
> @@ -156,7 +156,12 @@ typedef struct CXLEventDram {
> uint8_t row[3];
> uint16_t column;
> uint64_t correction_mask[4];
> - uint8_t reserved[0x17];
> + uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
> + uint8_t sub_channel;
> + uint8_t cme_ev_flags;
> + uint8_t cvme_count[3];
> + uint8_t sub_type;
> + uint8_t reserved;
> } QEMU_PACKED CXLEventDram;
>
> /*
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index d03a9f0edc29..3da538bafb64 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -1783,6 +1783,13 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
> #define CXL_DRAM_VALID_ROW BIT(5)
> #define CXL_DRAM_VALID_COLUMN BIT(6)
> #define CXL_DRAM_VALID_CORRECTION_MASK BIT(7)
> +#define CXL_DRAM_VALID_COMPONENT BIT(8)
> +#define CXL_DRAM_VALID_COMPONENT_ID_FORMAT BIT(9)
> +#define CXL_DRAM_VALID_SUB_CHANNEL BIT(10)
> +
> +#define CXL_DRAM_EV_DESC_UCE BIT(0)
> +#define CXL_DRAM_EV_DESC_THRESHOLD_EVENT BIT(1)
> +#define CXL_DRAM_EV_DESC_POISON_LIST_OVERFLOW_EVENT BIT(2)
>
> void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
> uint32_t flags,
> @@ -1802,6 +1809,12 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
> bool has_column, uint16_t column,
> bool has_correction_mask,
> uint64List *correction_mask,
> + const char *component_id,
> + bool has_comp_id_pldm, bool is_comp_id_pldm,
> + bool has_sub_channel, uint8_t sub_channel,
> + bool has_cme_ev_flags, uint8_t cme_ev_flags,
> + bool has_cvme_count, uint32_t cvme_count,
> + uint8_t sub_type,
> Error **errp)
> {
> Object *obj = object_resolve_path(path, NULL);
> @@ -1888,6 +1901,35 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
> valid_flags |= CXL_DRAM_VALID_CORRECTION_MASK;
> }
>
> + if (component_id) {
> + strncpy((char *)dram.component_id, component_id,
> + sizeof(dram.component_id) - 1);
> + valid_flags |= CXL_DRAM_VALID_COMPONENT;
> + if (has_comp_id_pldm && is_comp_id_pldm) {
> + valid_flags |= CXL_DRAM_VALID_COMPONENT_ID_FORMAT;
> + }
> + }
> +
> + if (has_sub_channel) {
> + dram.sub_channel = sub_channel;
> + valid_flags |= CXL_DRAM_VALID_SUB_CHANNEL;
> + }
> +
> + if (has_cme_ev_flags) {
> + dram.cme_ev_flags = cme_ev_flags;
> + } else {
> + dram.cme_ev_flags = 0;
> + }
> +
> + if (has_cvme_count) {
> + descriptor |= CXL_DRAM_EV_DESC_THRESHOLD_EVENT;
Same issue as the general media event patch - the modification to
'descriptor' is not written back to dram.descriptor which was assigned
earlier.
> + st24_le_p(dram.cvme_count, cvme_count);
> + } else {
> + st24_le_p(dram.cvme_count, 0);
> + }
> +
> + dram.sub_type = sub_type;
> +
> stw_le_p(&dram.validity_flags, valid_flags);
>
> if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&dram)) {
> diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c
> index 2047e9784694..231dda263fa4 100644
> --- a/hw/mem/cxl_type3_stubs.c
> +++ b/hw/mem/cxl_type3_stubs.c
> @@ -53,6 +53,13 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
> bool has_column, uint16_t column,
> bool has_correction_mask,
> uint64List *correction_mask,
> + const char *component_id,
> + bool has_comp_id_pldm,
> + bool is_comp_id_pldm,
> + bool has_sub_channel, uint8_t sub_channel,
> + bool has_cme_ev_flags, uint8_t cme_ev_flags,
> + bool has_cvme_count, uint32_t cvme_count,
> + uint8_t sub_type,
> Error **errp) {}
>
> void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
> --
> 2.48.1
>
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH qemu v4 5/5] hw/cxl/events: Updates for rev3.2 memory module event record
2026-01-19 11:15 ` [PATCH qemu v4 5/5] hw/cxl/events: Updates for rev3.2 memory module " Jonathan Cameron
@ 2026-02-04 21:46 ` Ravi Jonnalagadda
0 siblings, 0 replies; 13+ messages in thread
From: Ravi Jonnalagadda @ 2026-02-04 21:46 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Michael Tsirkin, qemu-devel, shiju.jose, armbru, linuxarm,
linux-cxl, Ravi Shankar
On Mon, Jan 19, 2026 at 3:18 AM Jonathan Cameron
<Jonathan.Cameron@huawei.com> wrote:
>
> From: Shiju Jose <shiju.jose@huawei.com>
>
> CXL spec rev3.2 section 8.2.10.2.1.3 Table 8-50, memory module
> event record has updated with following new fields.
> 1. Validity Flags
> 2. Component Identifier
> 3. Device Event Sub-Type
>
> Add updates for the above spec changes in the CXL memory module
> event reporting and QMP command to inject memory module event.
>
> Updated all references for this command to the CXL r3.2
> specification.
>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> ---
> v4: Update spec reference in the actual command as well (Markus)
> V3: Update spec references for whole command (Markus)
> ---
> qapi/cxl.json | 30 ++++++++++++++++++++----------
> include/hw/cxl/cxl_events.h | 7 +++++--
> hw/mem/cxl_type3.c | 20 ++++++++++++++++++++
> hw/mem/cxl_type3_stubs.c | 4 ++++
> 4 files changed, 49 insertions(+), 12 deletions(-)
>
> diff --git a/qapi/cxl.json b/qapi/cxl.json
> index 1dc8b08ca301..81d6198ba030 100644
> --- a/qapi/cxl.json
> +++ b/qapi/cxl.json
> @@ -214,20 +214,20 @@
> ##
> # @CXLMemModuleEvent:
> #
> -# Event record for a Memory Module Event (CXL r3.0 8.2.9.2.1.3).
> +# Event record for a Memory Module Event (CXL r3.2 8.2.10.2.1.3).
> #
> -# @type: Device Event Type. See CXL r3.0 Table 8-45 Memory Module
> +# @type: Device Event Type. See CXL r3.2 Table 8-59 Memory Module
> # Event Record for bit definitions for bit definiions.
> #
> -# @health-status: Overall health summary bitmap. See CXL r3.0 Table
> -# 8-100 Get Health Info Output Payload, Health Status for bit
> +# @health-status: Overall health summary bitmap. See CXL r3.2 Table
> +# 8-148 Get Health Info Output Payload, Health Status for bit
> # definitions.
> #
> -# @media-status: Overall media health summary. See CXL r3.0 Table
> -# 8-100 Get Health Info Output Payload, Media Status for bit
> +# @media-status: Overall media health summary. See CXL r3.2 Table
> +# 8-148 Get Health Info Output Payload, Media Status for bit
> # definitions.
> #
> -# @additional-status: See CXL r3.0 Table 8-100 Get Health Info Output
> +# @additional-status: See CXL r3.2 Table 8-148 Get Health Info Output
> # Payload, Additional Status for subfield definitions.
> #
> # @life-used: Percentage (0-100) of factory expected life span.
> @@ -243,6 +243,14 @@
> # @corrected-persistent-error-count: Total number of correctable
> # errors in persistent memory
> #
> +# @component-id: Device specific component identifier for the event.
> +# May describe a field replaceable sub-component of the device.
> +#
> +# @is-comp-id-pldm: This flag specifies whether the device-specific
> +# component identifier format follows PLDM.
> +#
> +# @sub-type: Device event sub-type.
> +#
> # Since: 8.1
> ##
> { 'struct': 'CXLMemModuleEvent',
> @@ -252,14 +260,16 @@
> 'life-used': 'uint8', 'temperature' : 'int16',
> 'dirty-shutdown-count': 'uint32',
> 'corrected-volatile-error-count': 'uint32',
> - 'corrected-persistent-error-count': 'uint32'
> + 'corrected-persistent-error-count': 'uint32',
> + '*component-id': 'str', '*is-comp-id-pldm':'bool',
> + 'sub-type':'uint8'
> }}
>
> ##
> # @cxl-inject-memory-module-event:
> #
> -# Inject an event record for a Memory Module Event (CXL r3.0
> -# 8.2.9.2.1.3). This event includes a copy of the Device Health info
> +# Inject an event record for a Memory Module Event (CXL r3.2
> +# 8.2.10.2.1.3). This event includes a copy of the Device Health info
> # at the time of the event.
> #
> # Since: 8.1
> diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h
> index a3c5f2ec20e6..4a7836ad7227 100644
> --- a/include/hw/cxl/cxl_events.h
> +++ b/include/hw/cxl/cxl_events.h
> @@ -166,7 +166,7 @@ typedef struct CXLEventDram {
>
> /*
> * Memory Module Event Record
> - * CXL r3.1 Section 8.2.9.2.1.3: Table 8-47
> + * CXL r3.2 Section 8.2.10.2.1.3: Table 8-59
Minor Nitpick : Table reference in commit message should match code
reference of Table 8-59
> * All fields little endian.
> */
> typedef struct CXLEventMemoryModule {
> @@ -180,7 +180,10 @@ typedef struct CXLEventMemoryModule {
> uint32_t dirty_shutdown_count;
> uint32_t corrected_volatile_error_count;
> uint32_t corrected_persistent_error_count;
> - uint8_t reserved[0x3d];
> + uint16_t validity_flags;
> + uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
> + uint8_t sub_type;
> + uint8_t reserved[0x2a];
> } QEMU_PACKED CXLEventMemoryModule;
>
> /*
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index 3da538bafb64..4dc9b223f476 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -1937,6 +1937,9 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
> }
> }
>
> +#define CXL_MMER_VALID_COMPONENT BIT(0)
> +#define CXL_MMER_VALID_COMPONENT_ID_FORMAT BIT(1)
> +
> void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
> uint32_t flags, bool has_maint_op_class,
> uint8_t maint_op_class,
> @@ -1953,11 +1956,16 @@ void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
> uint32_t dirty_shutdown_count,
> uint32_t corrected_volatile_error_count,
> uint32_t corrected_persist_error_count,
> + const char *component_id,
> + bool has_comp_id_pldm,
> + bool is_comp_id_pldm,
> + uint8_t sub_type,
> Error **errp)
> {
> Object *obj = object_resolve_path(path, NULL);
> CXLEventMemoryModule module;
> CXLEventRecordHdr *hdr = &module.hdr;
> + uint16_t valid_flags = 0;
> CXLDeviceState *cxlds;
> CXLType3Dev *ct3d;
> uint8_t enc_log;
> @@ -2000,6 +2008,18 @@ void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
> stl_le_p(&module.corrected_persistent_error_count,
> corrected_persist_error_count);
>
> + if (component_id) {
> + strncpy((char *)module.component_id, component_id,
> + sizeof(module.component_id) - 1);
> + valid_flags |= CXL_MMER_VALID_COMPONENT;
> + if (has_comp_id_pldm && is_comp_id_pldm) {
> + valid_flags |= CXL_MMER_VALID_COMPONENT_ID_FORMAT;
> + }
> + }
> + module.sub_type = sub_type;
> +
> + stw_le_p(&module.validity_flags, valid_flags);
> +
> if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&module)) {
> cxl_event_irq_assert(ct3d);
> }
> diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c
> index 231dda263fa4..98292a931c16 100644
> --- a/hw/mem/cxl_type3_stubs.c
> +++ b/hw/mem/cxl_type3_stubs.c
> @@ -78,6 +78,10 @@ void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
> uint32_t dirty_shutdown_count,
> uint32_t corrected_volatile_error_count,
> uint32_t corrected_persist_error_count,
> + const char *component_id,
> + bool has_comp_id_pldm,
> + bool is_comp_id_pldm,
> + uint8_t sub_type,
> Error **errp) {}
>
> void qmp_cxl_inject_poison(const char *path, uint64_t start, uint64_t length,
> --
> 2.48.1
>
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH qemu v4 3/5] hw/cxl/events: Updates for rev3.2 general media event record
2026-02-04 21:42 ` Ravi Jonnalagadda
@ 2026-02-05 10:58 ` Shiju Jose
0 siblings, 0 replies; 13+ messages in thread
From: Shiju Jose @ 2026-02-05 10:58 UTC (permalink / raw)
To: Ravi Jonnalagadda, Jonathan Cameron
Cc: Michael Tsirkin, qemu-devel@nongnu.org, armbru@redhat.com,
Linuxarm, linux-cxl@vger.kernel.org, Ravi Shankar
>-----Original Message-----
>From: Ravi Jonnalagadda <ravis.opensrc@gmail.com>
>Sent: 04 February 2026 21:42
>To: Jonathan Cameron <jonathan.cameron@huawei.com>
>Cc: Michael Tsirkin <mst@redhat.com>; qemu-devel@nongnu.org; Shiju Jose
><shiju.jose@huawei.com>; armbru@redhat.com; Linuxarm
><linuxarm@huawei.com>; linux-cxl@vger.kernel.org; Ravi Shankar
><venkataravis@micron.com>
>Subject: Re: [PATCH qemu v4 3/5] hw/cxl/events: Updates for rev3.2 general
>media event record
>
>On Mon, Jan 19, 2026 at 3:21 AM Jonathan Cameron
><Jonathan.Cameron@huawei.com> wrote:
>>
>> From: Shiju Jose <shiju.jose@huawei.com>
>>
>> CXL spec rev3.2 section 8.2.10.2.1.1 Table 8-57, general media event
>> table has updated with following new fields.
>> 1. Advanced Programmable Corrected Memory Error Threshold Event Flags
>> 2. Corrected Memory Error Count at Event 3. Memory Event Sub-Type 4.
>> Support for component ID in the PLDM format.
>>
>> Add updates for the above spec changes in the CXL general media event
>> reporting and QMP command to inject general media event.
>>
>> In order to have one consistent source of references, update all to
>> references for this command to CXL r3.2.
>>
>> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
>> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> ---
>> v4: Update the spec reference in the related command to 3.2 as well.
>> (Markus)
>> v3: Update all references to 3.2 for consistency.
>> ---
>> qapi/cxl.json | 29 +++++++++++++++++++++--------
>> include/hw/cxl/cxl_events.h | 7 +++++--
>> hw/mem/cxl_type3.c | 29 +++++++++++++++++++++++++++++
>> hw/mem/cxl_type3_stubs.c | 6 ++++++
>> 4 files changed, 61 insertions(+), 10 deletions(-)
>>
>> diff --git a/qapi/cxl.json b/qapi/cxl.json index
>> 82001c0591d8..4ff66fc6c16c 100644
>> --- a/qapi/cxl.json
>> +++ b/qapi/cxl.json
>>
>> stw_le_p(&gem.validity_flags, valid_flags);
>>
>> + if (has_cme_ev_flags) {
>> + gem.cme_ev_flags = cme_ev_flags;
>> + } else {
>> + gem.cme_ev_flags = 0;
>> + }
>> +
>> + if (has_cme_count) {
>> + descriptor |= CXL_GMER_EV_DESC_THRESHOLD_EVENT;
>
>The modification to 'descriptor' here is not written back to gem.descriptor which
>was assigned earlier in this function.
>
>Suggest moving gem.descriptor assignment after this block, similar to how
>valid_flags is handled in this same function.
>
Thanks Ravi.
Will fix.
>> void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
>> --
>> 2.48.1
>>
>>
Thanks,
Shiju
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2026-02-05 10:58 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
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2026-01-19 11:15 [PATCH qemu v4 0/5] cxl: r3.2 specification event updates Jonathan Cameron
2026-01-19 11:15 ` [PATCH qemu v4 1/5] qapi: cxl: Refactor CXL event injection for common commands arguments Jonathan Cameron
2026-02-04 21:34 ` Ravi Jonnalagadda
2026-01-19 11:15 ` [PATCH qemu v4 2/5] hw/cxl/events: Update for rev3.2 common event record format Jonathan Cameron
2026-02-04 21:35 ` Ravi Jonnalagadda
2026-01-19 11:15 ` [PATCH qemu v4 3/5] hw/cxl/events: Updates for rev3.2 general media event record Jonathan Cameron
2026-02-04 21:42 ` Ravi Jonnalagadda
2026-02-05 10:58 ` Shiju Jose
2026-01-19 11:15 ` [PATCH qemu v4 4/5] hw/cxl/events: Updates for rev3.2 DRAM " Jonathan Cameron
2026-02-04 21:44 ` Ravi Jonnalagadda
2026-01-19 11:15 ` [PATCH qemu v4 5/5] hw/cxl/events: Updates for rev3.2 memory module " Jonathan Cameron
2026-02-04 21:46 ` Ravi Jonnalagadda
2026-01-19 12:15 ` [PATCH qemu v4 0/5] cxl: r3.2 specification event updates Markus Armbruster
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