messages from 2023-06-15 16:41:46 to 2023-06-22 21:39:49 UTC [more...]
[PATCH v4 0/6] acpi: numa: add target support for generic port to HMAT parsing
2023-06-22 21:39 UTC (4+ messages)
` [PATCH v4 1/6] acpi: numa: Create enum for memory_target access coordinates indexing
` [PATCH v4 2/6] ACPICA: Add a define for size of acpi_srat_generic_affinity DeviceHandle
` [PATCH v4 3/6] acpi: numa: Add genport target allocation to the HMAT parsing
[PATCH v7 00/27] cxl/pci: Add support for RCH RAS error handling
2023-06-22 20:55 UTC (28+ messages)
` [PATCH v7 01/27] cxl/acpi: Probe RCRB later during RCH downstream port creation
` [PATCH v7 02/27] cxl: Updates for CXL Test to work with RCH
` [PATCH v7 03/27] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability
` [PATCH v7 04/27] cxl: Rename member @dport of struct cxl_dport to @dport_dev
` [PATCH v7 05/27] cxl: Rename 'uport' to 'uport_dev'
` [PATCH v7 06/27] cxl/core/regs: Add @dev to cxl_register_map
` [PATCH v7 07/27] cxl/pci: Refactor component register discovery for reuse
` [PATCH v7 08/27] cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs()
` [PATCH v7 09/27] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port
` [PATCH v7 10/27] cxl/port: Remove Component Register base address from struct cxl_dport
` [PATCH v7 11/27] cxl/regs: Remove early capability checks in Component Register setup
` [PATCH v7 12/27] cxl/mem: Prepare for early RCH dport component register setup
` [PATCH v7 13/27] cxl/pci: Early setup RCH dport component registers from RCRB
` [PATCH v7 14/27] cxl/port: Store the port's Component Register mappings in struct cxl_port
` [PATCH v7 15/27] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport
` [PATCH v7 16/27] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state
` [PATCH v7 17/27] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
` [PATCH v7 18/27] cxl/port: Remove Component Register base address from struct cxl_port
` [PATCH v7 19/27] cxl/pci: Add RCH downstream port AER register discovery
` [PATCH v7 20/27] PCI/AER: Refactor cper_print_aer() for use by CXL driver module
` [PATCH v7 21/27] cxl/pci: Update CXL error logging to use RAS register address
` [PATCH v7 22/27] cxl/pci: Map RCH downstream AER registers for logging protocol errors
` [PATCH v7 23/27] cxl/pci: Add RCH downstream port error logging
` [PATCH v7 24/27] cxl/pci: Disable root port interrupts in RCH mode
` [PATCH v7 25/27] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler
` [PATCH v7 26/27] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling
` [PATCH v7 27/27] cxl/core/regs: Rename phys_addr in cxl_map_component_regs()
[PATCH v3 0/6] acpi: numa: add target support for generic port to HMAT parsing
2023-06-22 18:41 UTC (12+ messages)
` [PATCH v3 1/6] acpi: numa: Create enum for memory_target access coordinates indexing
` [PATCH v3 2/6] ACPICA: Add a define for size of acpi_srat_generic_affinity DeviceHandle
` [PATCH v3 3/6] acpi: numa: Add genport target allocation to the HMAT parsing
` [PATCH v3 4/6] acpi: Break out nesting for hmat_parse_locality()
` [PATCH v3 5/6] acpi: numa: Add setting of generic port system locality attributes
` [PATCH v3 6/6] acpi: numa: Add helper function to retrieve the performance attributes
[PATCH 0/5] cxl/dcd: Add support for Dynamic Capacity Devices (DCD)
2023-06-22 17:01 UTC (42+ messages)
` [PATCH 1/5] cxl/mem : Read Dynamic capacity configuration from the device
` [PATCH 2/5] cxl/region: Add dynamic capacity cxl region support
` [PATCH 3/5] cxl/mem : Expose dynamic capacity configuration to userspace
` [PATCH 4/5] cxl/mem: Add support to handle DCD add and release capacity events
` [PATCH 5/5] cxl/mem: Trace Dynamic capacity Event Record
[PATCH v6 00/27] cxl/pci: Add support for RCH RAS error handling
2023-06-22 16:33 UTC (43+ messages)
` [PATCH v6 01/27] cxl/port: Fix NULL pointer access in devm_cxl_add_port()
` [PATCH v6 02/27] cxl/acpi: Probe RCRB later during RCH downstream port creation
` [PATCH v6 03/27] cxl: Updates for CXL Test to work with RCH
` [PATCH v6 04/27] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability
` [PATCH v6 05/27] cxl: Rename member @dport of struct cxl_dport to @dport_dev
` [PATCH v6 06/27] cxl: Rename 'uport' to 'uport_dev'
` [PATCH v6 07/27] cxl/core/regs: Add @dev to cxl_register_map
` [PATCH v6 08/27] cxl/pci: Refactor component register discovery for reuse
` [PATCH v6 09/27] cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs()
` [PATCH v6 10/27] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port
` [PATCH v6 11/27] cxl/port: Remove Component Register base address from struct cxl_dport
` [PATCH v6 12/27] cxl/regs: Remove early capability checks in Component Register setup
` [PATCH v6 13/27] cxl/mem: Prepare for early RCH dport component register setup
` [PATCH v6 14/27] cxl/pci: Early setup RCH dport component registers from RCRB
` [PATCH v6 15/27] cxl/port: Store the port's Component Register mappings in struct cxl_port
` [PATCH v6 16/27] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport
` [PATCH v6 17/27] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state
` [PATCH v6 18/27] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
` [PATCH v6 19/27] cxl/port: Remove Component Register base address from struct cxl_port
` [PATCH v6 20/27] cxl/pci: Add RCH downstream port AER register discovery
` [PATCH v6 21/27] PCI/AER: Refactor cper_print_aer() for use by CXL driver module
` [PATCH v6 22/27] cxl/pci: Update CXL error logging to use RAS register address
` [PATCH v6 23/27] cxl/pci: Map RCH downstream AER registers for logging protocol errors
` [PATCH v6 24/27] cxl/pci: Add RCH downstream port error logging
` [PATCH v6 25/27] cxl/pci: Disable root port interrupts in RCH mode
` [PATCH v6 26/27] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler
` [PATCH v6 27/27] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling
[BUG] Root port fails to match with port driver on non-RCH topology
2023-06-22 14:47 UTC (6+ messages)
[PATCH v2 00/12] Device memory prep
2023-06-22 14:04 UTC (22+ messages)
` [PATCH v2 03/12] cxl: Fix kernel-doc warnings
` [PATCH v2 04/12] cxl: Remove leftover attribute documentation in 'struct cxl_dev_state'
` [PATCH v2 06/12] cxl/memdev: Make mailbox functionality optional
` [PATCH v2 07/12] cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}
` [PATCH v2 08/12] cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEM
` [PATCH v2 10/12] cxl/pci: Unconditionally unmask 256B Flit errors
` [PATCH v2 11/12] cxl/port: Enumerate cxl link capabilities
[PATCH 0/3] mm: use memmap_on_memory semantics for dax/kmem
2023-06-22 13:55 UTC (14+ messages)
` [PATCH 1/3] mm/memory_hotplug: Allow an override for the memmap_on_memory param
` [PATCH 2/3] mm/memory_hotplug: Export symbol mhp_supports_memmap_on_memory()
` [PATCH 3/3] dax/kmem: Always enroll hotplugged memory for memmap_on_memory
[PATCH v7 00/11] cxl: Add support for QTG ID retrieval for CXL subsystem
2023-06-22 13:28 UTC (13+ messages)
` [PATCH v7 01/11] cxl: Add callback to parse the DSMAS subtables from CDAT
` [PATCH v7 02/11] cxl: Add callback to parse the DSLBIS subtable "
` [PATCH v7 03/11] cxl: Add callback to parse the SSLBIS "
` [PATCH v7 04/11] cxl: Add support for _DSM Function for retrieving QTG ID
` [PATCH v7 05/11] cxl: Calculate and store PCI link latency for the downstream ports
` [PATCH v7 06/11] cxl: Store the access coordinates for the generic ports
` [PATCH v7 07/11] cxl: Add helper function that calculate performance data for downstream ports
` [PATCH v7 08/11] cxl: Compute the entire CXL path latency and bandwidth data
` [PATCH v7 09/11] cxl: Store QTG IDs and related info to the CXL memory device context
` [PATCH v7 10/11] cxl: Export sysfs attributes for memory device QoS class
` [PATCH v7 11/11] cxl/mem: Add debugfs output for QTG related data
[PATCH] Revert "cxl/port: Enable the HDM decoder capability for switch ports"
2023-06-22 9:22 UTC (3+ messages)
[PATCH 0/3] cxl/region: Cache management and region decode reset fixes
2023-06-22 9:18 UTC (10+ messages)
` [PATCH 1/3] cxl/region: Move cache invalidation before region teardown, and before setup
` [PATCH 2/3] cxl/region: Flag partially torn down regions as unusable
` [PATCH 3/3] cxl/region: Fix state transitions after reset failure
[PATCH] dax/kmem: Pass valid argument to memory_group_register_static
2023-06-22 7:15 UTC (5+ messages)
[PATCH v3] dax/kmem: Pass valid argument to memory_group_register_static
2023-06-21 15:50 UTC
[PATCH v2] dax/kmem: Pass valid argument to memory_group_register_static
2023-06-21 10:34 UTC
Questions on getting started
2023-06-20 21:16 UTC (4+ messages)
[PATCH v4 0/4] acpi: Add CDAT parsing support to ACPI tables code
2023-06-19 7:40 UTC (3+ messages)
` [PATCH v4 1/4] acpi: Move common tables helper functions to common lib
CXL/region : commit reset of out of order region appears to succeed
2023-06-17 0:26 UTC (2+ messages)
[PATCH 0/4] dax: Fix use after free and other cleanups
2023-06-16 22:11 UTC (11+ messages)
` [PATCH 1/4] dax: Fix dax_mapping_release() use after free
` [PATCH 2/4] dax: Use device_unregister() in unregister_dax_mapping()
` [PATCH 3/4] dax: Introduce alloc_dev_dax_id()
` [PATCH 4/4] dax: Cleanup extra dax_region references
[PATCH] dax: include bus.h for definition of run_dax()
2023-06-16 18:25 UTC (2+ messages)
[PATCH v5 00/26] cxl/pci: Add support for RCH RAS error handling
2023-06-16 16:28 UTC (5+ messages)
` [PATCH v5 24/26] cxl/pci: Add RCH downstream port error logging
[ndctl PATCH 0/2] Fix accessors for temperature field when it is negative
2023-06-16 1:08 UTC (3+ messages)
` [ndctl PATCH 1/2] cxl: Update a revision by CXL 3.0 specification
` [ndctl PATCH 2/2] libcxl: Fix accessors for temperature field to support negative value
[ndctl PATCH v2 1/2] cxl/list: Add parent_dport attribute to memdev and root port listing
2023-06-15 16:40 UTC (2+ messages)
` [ndctl PATCH v2 2/2] cxl-graph: Add cxl graph command to construct CXL topology graph images
[ndctl PATCH v2 0/2] cxl-graph: add a new command to construct CXL topology graph images
2023-06-15 16:40 UTC
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