From: Gregory Price <gregory.price@memverge.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Gregory Price <gourry.memverge@gmail.com>,
qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, mst@redhat.com,
marcel.apfelbaum@gmail.com, imammedo@redhat.com, ani@anisinha.ca,
alison.schofield@intel.com, dave@stgolabs.net,
a.manzanares@samsung.com, bwidawsk@kernel.org,
hchkuo@avery-design.com.tw, cbrowy@avery-design.com,
ira.weiny@intel.com
Subject: Re: [PATCH 3/4] hw/cxl: Multi-Region CXL Type-3 Devices (Volatile and Persistent)
Date: Wed, 23 Nov 2022 12:42:29 -0500 [thread overview]
Message-ID: <Y35bhWf9qAQklDRU@memverge.com> (raw)
In-Reply-To: <20221114175341.000036c4@Huawei.com>
> > - -object memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest.raw,size=256M \
> > - -object memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa.raw,size=256M \
> > + -object memory-backend-file,pmem=true,id=pmem0,share=on,mem-path=/tmp/cxltest.raw,size=256M \
> > + -object memory-backend-file,pmem=true,id=cxl-lsa0,share=on,mem-path=/tmp/lsa.raw,size=256M \
>
> Why make the pmem=true change in here? If we want to do that I think it should be in a
> separate patch with explanation.
>
this is mostly an observation that memory-backend's have a pmem option.
It was unclear to me that using this backend for a pmem region without
setting pmem=true was "correct", but i also am not sure it has a real
effect. I'll drop this from the changeset.
> > +error_cleanup:
> > + int i;
> > + for (i = 0; i < cur_ent; i++) {
> > + g_free(*cdat_table[i]);
>
> Until the steal pointer above, *cdata_table not set to anything.
> Possibly gfree(table[i])?
>
>
good catch
> Hmm. I wonder if this is simpler done as below. Both look fine
> to me though so up to you for next version. Trade off between
> slightly ugly nested logic, and the readability always lost when
> a ternary operator puts in an appearance.
>
> if (ct3d->hostvmem) {
this seems reasonable, pulled in
>
> If we have both volatile and persistent and yet still only have our one HDM
> decoder, then I think a write into the persistent range will have the wrong offset.
>
> dpa_offset == address space offset when we only had one region. Not so much any more.
> For persistent i think we'll need to subtract the size of the volatile region
> (possibly taking care with alignment - I need to check that).
>
I had originally done this, but it wasn't clear to me what was correct
here, I'll make the adjustment
> > diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c
> > index 6baed747fa..a05ddc0c7b 100644
> > --- a/tests/qtest/cxl-test.c
> > +++ b/tests/qtest/cxl-test.c
> > @@ -34,29 +34,46 @@
> > - "-object memory-backend-file,id=cxl-mem3,mem-path=%s,size=256M " \
> > - "-object memory-backend-file,id=lsa3,mem-path=%s,size=256M " \
> > - "-device cxl-type3,bus=rp3,memdev=cxl-mem3,lsa=lsa3,id=cxl-pmem3 "
>
> If re-indenting makes sense (I'm really convinced it is worth the noise) then do it
> in a precusor no-op patch so we can more easily see what is new here.)
>
can do
next prev parent reply other threads:[~2022-11-23 17:42 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20221026004835uscas1p1d37255ba8daaba8fc7e16e5129cb94b5@uscas1p1.samsung.com>
2022-10-26 0:47 ` [PATCH 0/4 v3] Multi-Region and Volatile Memory support for CXL Type-3 Devices Gregory Price
2022-10-26 0:47 ` [PATCH 1/4] hw/i386/pc.c: CXL Fixed Memory Window should not reserve e820 in bios Gregory Price
2022-10-26 20:33 ` Michael S. Tsirkin
2022-10-26 0:47 ` [PATCH 2/4] hw/cxl: Add CXL_CAPACITY_MULTIPLIER definition Gregory Price
2022-11-14 17:55 ` Jonathan Cameron
2022-10-26 0:47 ` [PATCH 3/4] hw/cxl: Multi-Region CXL Type-3 Devices (Volatile and Persistent) Gregory Price
2022-11-14 17:53 ` Jonathan Cameron
2022-11-14 23:00 ` Gregory Price
2022-11-17 13:53 ` Jonathan Cameron
2022-11-23 17:42 ` Gregory Price [this message]
2022-10-26 0:47 ` [PATCH 4/4] hw/acpi/cxl.c: Fill in SRAT for vmem/pmem if NUMA node is assigned Gregory Price
2022-10-26 20:13 ` [PATCH 0/4 v3] Multi-Region and Volatile Memory support for CXL Type-3 Devices Adam Manzanares
2022-10-26 20:47 ` Gregory Price
2022-10-27 10:58 ` Jonathan Cameron
2022-10-27 14:29 ` Gregory Price
2022-10-27 18:10 ` Adam Manzanares
2022-10-26 20:15 ` Michael S. Tsirkin
2022-10-26 20:20 ` Michael S. Tsirkin
2022-10-26 20:48 ` Gregory Price
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