From: Gregory Price <gourry@gourry.net>
To: Robert Richter <rrichter@amd.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Jonathan Cameron <jonathan.cameron@huawei.com>,
Dave Jiang <dave.jiang@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 0/5] Address translation for HDM decoding
Date: Thu, 25 Jul 2024 18:00:00 -0400 [thread overview]
Message-ID: <ZqLK4CpSg4PfAdGx@PC2K9PVX.TheFacebook.com> (raw)
In-Reply-To: <20240701174754.967954-1-rrichter@amd.com>
On Mon, Jul 01, 2024 at 07:47:48PM +0200, Robert Richter wrote:
> Default expectation of Linux is that HPA == SPA, which means that
> hardware addresses in the decoders are the same as the kernel sees
> them. However, there are platforms where this is not the case and an
> address translation between decoder's (HPA) and the system's physical
> addresses (SPA) is needed.
>
> This series implements address translation for HDM decoding. The
> implementation follows the rule that the representation of hardware
> address ranges in the kernel are all SPA. If decoder registers (HDM
> decoder cap or register range) are not SPA, a base offset must be
> applied. Translation happens when accessing the registers back and
> forth. After a read access an address will be converted to SPA and
> before a write access the programmed address is translated from an
> SPA. The decoder register access can be easily encapsulated by address
> translation and thus there are only a few places where translation is
> needed and the code must be changed. This is implemented in patch #2,
> patch #1 is a prerequisite.
>
> Address translation is restricted to platforms that need it. As such a
> platform check is needed and a flag is introduced for this (patch #3).
>
> For address translation the base offset must be determined for the
> memory domain. Depending on the platform there are various options for
> this. The address range in the CEDT's CFWMS entry of the CXL host
> bridge can be used to determine the decoder's base address (patch
> #4). This is enabled for AMD Zen4 platforms (patch #5).
>
> Changelog:
>
> v2:
> * Fixed build error for other archs [kbot]
>
Hi Robert,
I'm looking to test this patch series but saw you were looking at
reworking a portion of it. Just wanted to inquire as to whether
you think I should wait for a v3 given this is a few weeks old now.
Thanks!
~Gregory
next prev parent reply other threads:[~2024-07-25 22:00 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-01 17:47 [PATCH v2 0/5] Address translation for HDM decoding Robert Richter
2024-07-01 17:47 ` [PATCH v2 1/5] cxl/hdm: Moving HDM specific code to core/hdm.c Robert Richter
2024-07-12 0:32 ` Dan Williams
2024-07-01 17:47 ` [PATCH v2 2/5] cxl/hdm: Implement address translation for HDM decoding Robert Richter
2024-07-12 1:03 ` Dan Williams
2024-07-13 7:40 ` Robert Richter
2024-07-01 17:47 ` [PATCH v2 3/5] cxl/acpi: Add platform flag for HPA address translation Robert Richter
2024-07-12 1:27 ` Dan Williams
2024-07-13 7:41 ` Robert Richter
2024-07-01 17:47 ` [PATCH v2 4/5] cxl/hdm: Setup HPA base for address translation using the HPA window in CFMWS Robert Richter
2024-07-01 17:47 ` [PATCH v2 5/5] cxl/acpi: Enable address translation for Zen4 platforms Robert Richter
2024-07-11 0:02 ` [PATCH v2 0/5] Address translation for HDM decoding Alison Schofield
2024-07-11 0:26 ` Alison Schofield
2024-07-11 19:03 ` Robert Richter
2024-07-25 22:00 ` Gregory Price [this message]
2024-08-06 10:54 ` Robert Richter
2024-08-16 18:32 ` Gregory Price
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