From: Gregory Price <gourry@gourry.net>
To: Huang Ying <ying.huang@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>,
Dave Jiang <dave.jiang@intel.com>,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Alejandro Lucero <alucerop@amd.com>
Subject: Re: [RFC 3/5] cxl: Separate coherence from target type
Date: Tue, 1 Oct 2024 09:53:09 -0400 [thread overview]
Message-ID: <Zvv-xTGGTZee_fr8@PC2K9PVX.TheFacebook.com> (raw)
In-Reply-To: <20240925024647.46735-4-ying.huang@intel.com>
On Wed, Sep 25, 2024 at 10:46:45AM +0800, Huang Ying wrote:
> Previously, target type (expander or accelerator) and
> coherence (HOSTONLY (HDM-H) or DEV (HDM-D/DB)) are synonym. So target
> type is used to designate coherence too. However, it's possible for
> expanders to use HDM-DB now. So, we need to separate coherence from
> target type.
>
> Accordingly, the HOSTONLY field of decoder ctrl
> register (CXL_HDM_DECODER0_CTRL_HOSTONLY) need to be set according to
> coherence.
>
> The coherence of decoders can not be determined via target type too.
> So, accelerator/expander device drivers need to specify coherence
> explicitly via newly added coherence field in struct cxl_dev_state.
>
> The coherence of each end points in a region need to be same. So, the
> coherence of the first end point is recorded in struct region. Which
> will be checked against the coherence of all other end points.
>
> Signed-off-by: "Huang, Ying" <ying.huang@intel.com>
> Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Cc: Dan Williams <dan.j.williams@intel.com>
> Cc: Davidlohr Bueso <dave@stgolabs.net>
> Cc: Jonathan Cameron <jonathan.cameron@huawei.com>
> Cc: Dave Jiang <dave.jiang@intel.com>
> Cc: Alison Schofield <alison.schofield@intel.com>
> Cc: Vishal Verma <vishal.l.verma@intel.com>
> Cc: Ira Weiny <ira.weiny@intel.com>
> Cc: Alejandro Lucero <alucerop@amd.com>
> ---
> drivers/cxl/core/hdm.c | 22 +++++++++++++++-------
> drivers/cxl/core/mbox.c | 1 +
> drivers/cxl/core/port.c | 1 +
> drivers/cxl/core/region.c | 37 ++++++++++++++++++++++++++++++++++---
> drivers/cxl/cxl.h | 9 +++++++++
> drivers/cxl/cxlmem.h | 11 +++++++++++
> 6 files changed, 71 insertions(+), 10 deletions(-)
>
Reviewed-by: Gregory Price <gourry@gourry.net>
> @@ -1925,6 +1933,29 @@ static int cxl_region_attach(struct cxl_region *cxlr,
> return -ENXIO;
> }
>
> + /* Set the coherence of region to that of the first endpoint */
> + if (cxlr->coherence == CXL_DECODER_INVALIDCOH) {
> + unsigned long flags = cxlrd->cxlsd.cxld.flags;
> + enum cxl_decoder_coherence coherence = cxled->cxld.coherence;
> +
> + cxlr->coherence = coherence;
> + if ((coherence == CXL_DECODER_HOSTONLYCOH &&
> + !(flags & CXL_DECODER_F_HOSTONLYCOH)) ||
> + (coherence == CXL_DECODER_DEVCOH &&
> + !(flags & CXL_DECODER_F_DEVCOH))) {
silly nit but my gut tells me we can make this less ugly.
Not a blocker though.
> + dev_dbg(&cxlr->dev,
> +"%s:%s endpoint coherence: %d isn't supported by root decoder: %#lx\n",
> + dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev),
> + coherence, flags);
> + return -ENXIO;
> + }
next prev parent reply other threads:[~2024-10-01 13:53 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-25 2:46 [RFC 0/5] cxl: Preparation of type2 accelerators support Huang Ying
2024-09-25 2:46 ` [RFC 1/5] cxl: Rename ACPI_CEDT_CFMWS_RESTRICT_TYPE2/TYPE3 Huang Ying
2024-10-01 2:48 ` Davidlohr Bueso
2024-10-01 13:43 ` Gregory Price
2024-09-25 2:46 ` [RFC 2/5] cxl: Rename CXL_DECODER_HOSTONLYMEM/DEVMEM Huang Ying
2024-10-01 3:01 ` Davidlohr Bueso
2024-10-01 13:45 ` Gregory Price
2024-09-25 2:46 ` [RFC 3/5] cxl: Separate coherence from target type Huang Ying
2024-10-01 13:53 ` Gregory Price [this message]
2024-10-02 0:41 ` Huang, Ying
2024-10-11 2:40 ` Huang, Ying
2024-10-02 21:15 ` Ben Cheatham
2024-10-03 1:13 ` Huang, Ying
2024-09-25 2:46 ` [RFC 4/5] cxl: Set type of region to that of the first endpoint Huang Ying
2024-10-01 13:56 ` Gregory Price
2024-10-02 0:40 ` Huang, Ying
2024-10-02 21:15 ` Ben Cheatham
2024-10-03 1:12 ` Huang, Ying
2024-10-03 14:28 ` Ben Cheatham
2024-09-25 2:46 ` [RFC 5/5] cxl: Avoid to create dax regions for type2 accelerators Huang Ying
2024-10-01 13:57 ` Gregory Price
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