From: Ben Cheatham <benjamin.cheatham@amd.com>
To: "Huang, Ying" <ying.huang@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
"Jonathan Cameron" <Jonathan.Cameron@huawei.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Alejandro Lucero <alucerop@amd.com>,
Dan Williams <dan.j.williams@intel.com>,
Dave Jiang <dave.jiang@intel.com>
Subject: Re: [RFC 4/5] cxl: Set type of region to that of the first endpoint
Date: Thu, 3 Oct 2024 09:28:07 -0500 [thread overview]
Message-ID: <9d6fc7c9-e94e-48e2-8c41-b6bbf5e1e3cd@amd.com> (raw)
In-Reply-To: <87a5fmng5z.fsf@yhuang6-desk2.ccr.corp.intel.com>
On 10/2/24 8:12 PM, Huang, Ying wrote:
> Hi, Ben,
>
> Ben Cheatham <benjamin.cheatham@amd.com> writes:
>
>> On 9/24/24 9:46 PM, Huang Ying wrote:
>
> [snip]
>
>>> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
>>> index 2dee78e9b90c..5633b7316cb3 100644
>>> --- a/drivers/cxl/core/port.c
>>> +++ b/drivers/cxl/core/port.c
>>> @@ -139,6 +139,8 @@ static ssize_t target_type_show(struct device *dev,
>>> return sysfs_emit(buf, "accelerator\n");
>>> case CXL_DECODER_EXPANDER:
>>> return sysfs_emit(buf, "expander\n");
>>> + default:
>>> + break;
>>
>> You can drop this imo. It doesn't change anything functionally considering
>> the break is immediately followed by a return.
>
> Sorry, I cannot do that. Otherwise, there will be build error.
>
I thought that might be the case, but figured I'd suggest it anyway. Oh well!
Thanks,
Ben
>> Thanks,
>> Ben
>>
>>> }
>>> return -ENXIO;
>>> }
>
> [snip]
>
> --
> Best Regards,
> Huang, Ying
next prev parent reply other threads:[~2024-10-03 14:28 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-25 2:46 [RFC 0/5] cxl: Preparation of type2 accelerators support Huang Ying
2024-09-25 2:46 ` [RFC 1/5] cxl: Rename ACPI_CEDT_CFMWS_RESTRICT_TYPE2/TYPE3 Huang Ying
2024-10-01 2:48 ` Davidlohr Bueso
2024-10-01 13:43 ` Gregory Price
2024-09-25 2:46 ` [RFC 2/5] cxl: Rename CXL_DECODER_HOSTONLYMEM/DEVMEM Huang Ying
2024-10-01 3:01 ` Davidlohr Bueso
2024-10-01 13:45 ` Gregory Price
2024-09-25 2:46 ` [RFC 3/5] cxl: Separate coherence from target type Huang Ying
2024-10-01 13:53 ` Gregory Price
2024-10-02 0:41 ` Huang, Ying
2024-10-11 2:40 ` Huang, Ying
2024-10-02 21:15 ` Ben Cheatham
2024-10-03 1:13 ` Huang, Ying
2024-09-25 2:46 ` [RFC 4/5] cxl: Set type of region to that of the first endpoint Huang Ying
2024-10-01 13:56 ` Gregory Price
2024-10-02 0:40 ` Huang, Ying
2024-10-02 21:15 ` Ben Cheatham
2024-10-03 1:12 ` Huang, Ying
2024-10-03 14:28 ` Ben Cheatham [this message]
2024-09-25 2:46 ` [RFC 5/5] cxl: Avoid to create dax regions for type2 accelerators Huang Ying
2024-10-01 13:57 ` Gregory Price
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