Re: [PATCH v8 05/11] cxl: Defer dport allocation for switch ports

[Robert Richter <rrichter@amd.com>]

On 20.08.25 08:20:04, Dave Jiang wrote:
> On 8/20/25 5:41 AM, Robert Richter wrote:
> > Hi Dave,
> > 
> > see my comments below.
> > 
> > On 14.08.25 15:21:45, Dave Jiang wrote:
> 
> <--snip-->
>  
> >> +	if (IS_ERR(new_dport))
> >> +		return new_dport;
> >> +
> >> +	cxl_switch_parse_cdat(port);
> >> +
> >> +	/*
> >> +	 * First instance of dport appearing, need to setup the port, including
> >> +	 * allocating decoders.
> >> +	 */
> >> +	if (port->nr_dports == 1) {
> >> +		rc = cxl_switch_port_setup(port);
> > 
> > Can't this be done with port creation? I don't see a reason doing this
> > late at this point.
> 

> The main reason we are doing this is to move the port register
> probing until we know the CXL link is established. Otherwise when
> cxl_acpi does probe and calls add_host_bridge_uport(), that
> devm_cxl_add_port() can trigger errors if the platform BIOS enables
> PCI hotplug support on Intel platforms. The error messages "cxl
> portN: Couldn't locate the CXL.cache and CXL.mem capability array
> header" is observed. Essentially we can be trying to map registers
> while DVSEC ID 3 and/or 7 has not appeared yet. And in turn because
> that got pushed out, so did the decoder enumeration.

The code suggests the Component Registers of the CXL Host Bridge are
not yet ready. Is this delayed after the first Root Port is connected
to a CXL Endpoint/Switch? PCIe DVSEC ID 3 and 7
(CXL_DVSEC_PORT_EXTENSIONS, CXL_DVSEC_PCIE_FLEXBUS_PORT) are part of
the pcie config space, which is enumerated not before a CXL endpoint
becomes active. I haven't found a spec refs here. Please explain.

Thanks,

-Robert