From: Robert Richter <rrichter@amd.com>
To: Alison Schofield <alison.schofield@intel.com>
Cc: Davidlohr Bueso <dave@stgolabs.net>,
Jonathan Cameron <jic23@kernel.org>,
Dave Jiang <dave.jiang@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <iweiny@kernel.org>, Dan Williams <djbw@kernel.org>,
Li Ming <ming.li@zohomail.com>,
linux-cxl@vger.kernel.org
Subject: Re: [PATCH v2 3/6] cxl/region: Account for mixed-granularity in position calculations
Date: Mon, 29 Jun 2026 08:41:06 +0200 [thread overview]
Message-ID: <akITgju_8_6PoKFB@rric.localdomain> (raw)
In-Reply-To: <94ec26d420e0e40a2a991c1a4205e9e93cab44de.1781199122.git.alison.schofield@intel.com>
Alison,
On 11.06.26 10:47:27, Alison Schofield wrote:
> Mixed-granularity regions place the root decoder at outer HPA bits.
> A root target then owns root_gran / region_gran inner positions
> before the root advances to the next target. That ratio becomes the
> root target stride in region positions.
>
> Account for that stride in endpoint placement, position calculation,
> and peer-distance checks.
I don't see why root decoders need special handling here (apart from
the 3-way factor, but this is already handled). See my earlier
comments to the other patches, but if root decoders were just included
in the pos calculation, that should give correct results. And, instead
of introducing the "stride" term, why not just continue to work with
the selector mask also for the root decoders?
This "special case" handling unnecessarily introduces complex logic
and code. We should avoid that.
-Robert
>
> Remove the temporary mixed-granularity attach reject now that position
> arithmetic matches the selector layout.
>
> Signed-off-by: Alison Schofield <alison.schofield@intel.com>
> ---
> drivers/cxl/core/region.c | 79 ++++++++++++++++++++++++++++-----------
> 1 file changed, 58 insertions(+), 21 deletions(-)
next prev parent reply other threads:[~2026-06-29 6:41 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-11 17:47 [PATCH v2 0/6] cxl: Support mixed-granularity region interleaves Alison Schofield
2026-06-11 17:47 ` [PATCH v2 1/6] cxl/region: Validate interleave selector bits Alison Schofield
2026-06-26 11:37 ` Robert Richter
2026-06-26 15:21 ` Robert Richter
2026-07-08 2:05 ` Alison Schofield
2026-07-08 2:00 ` Alison Schofield
2026-06-11 17:47 ` [PATCH v2 2/6] cxl/region: Derive port granularity from " Alison Schofield
2026-06-26 12:09 ` Robert Richter
2026-07-08 2:09 ` Alison Schofield
2026-06-11 17:47 ` [PATCH v2 3/6] cxl/region: Account for mixed-granularity in position calculations Alison Schofield
2026-06-11 18:01 ` sashiko-bot
2026-06-12 6:21 ` Richard Cheng
2026-06-17 3:10 ` Alison Schofield
2026-06-29 6:41 ` Robert Richter [this message]
2026-07-08 1:43 ` Alison Schofield
2026-06-11 17:47 ` [PATCH v2 4/6] cxl/region: Validate mixed-granularity at sysfs and attach gates Alison Schofield
2026-06-11 18:03 ` sashiko-bot
2026-06-16 22:52 ` Alison Schofield
2026-06-11 17:47 ` [PATCH v2 5/6] cxl/test: Add a topology to test mixed-granularity regions Alison Schofield
2026-06-11 17:47 ` [PATCH v2 6/6] Documentation/cxl: Add region granularity and multi-level interleave guide Alison Schofield
2026-06-29 8:56 ` Robert Richter
2026-07-08 2:33 ` Alison Schofield
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