Re: [PATCH v30 1/2] cxl: Support Type2 cxl regs mapping

Re: [PATCH v30 1/2] cxl: Support Type2 cxl regs mapping

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The commit claims to export core functions for a Type2 driver to discover and map device registers, but it fails to expose the mapping functions in a public header.
--

commit e264e4eb8d1791f45613794c005249488536d8e2
Author: Alejandro Lucero <alucerop@amd.com>

cxl: Support Type2 cxl regs mapping

This commit creates a new public header file for CXL PCI definitions. It
exports the register setup function and register block identifier enum so
that out-of-subsystem Type2 drivers can discover device registers.

> Export cxl core functions for a Type2 driver being able to discover and
> map the device registers.

[ ... ]

> diff --git a/include/cxl/pci.h b/include/cxl/pci.h
> new file mode 100644
> index 0000000000000..3e0000015871a
> --- /dev/null
> +++ b/include/cxl/pci.h
> @@ -0,0 +1,22 @@

[ ... ]

> +struct cxl_register_map;
> +struct pci_dev;
> +
> +int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
> +		       struct cxl_register_map *map);
> +#endif

[Severity: Medium]
The commit message mentions exporting functions to both discover and map device
registers, but are the mapping functions missing from this public header?

While cxl_pci_setup_regs() is exposed here for register discovery, the
functions needed to map those registers, cxl_map_component_regs() and
cxl_map_device_regs(), appear to remain unexported in the private
drivers/cxl/cxl.h header.

Does this regression prevent a Type 2 driver outside of drivers/cxl/ from
cleanly calling the mapping functions without duplicating prototypes or
violating subsystem boundaries?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260629183727.51502-1-alejandro.lucero-palau@amd.com?part=1

Re: [PATCH v30 0/2] Type2 device basic support

[Dave Jiang]

On 6/29/26 11:37 AM, alejandro.lucero-palau@amd.com wrote:
> From: Alejandro Lucero <alucerop@amd.com>
> 
> This series adds the last bits for allowing a CXL Type2 driver to obtain
> a CXL region linked to the device HDM decoders committed by the BIOS.
> 
> For the sake of merging those changes and the driver using them, this
> version only adds the changes without a client. A later series will
> include sfc netdev driver as the client.
> 
> Changes from v29:
> 
>  - Only cxl core changes.
> 
> Changes from v28:
> 
>  - patch 1:
>         fix doc (Ed Cree)
>         fix error path (Sashiko)
> 
>  - patch 3:
>         removing extra + char (sashiko)
> 
>  - path5:
>         remove stray change (Ed Cree)
> 
> Changes from v27:
> 
>  - patch 1: make driver probe failing if error in efx_cxl_init (Dan)
>  - patch 4: add unmapping if error after efx_cxl_init (Dave)
>  - patch 4/5: move cxl_pio_initialised from patch 4 to patch 5 (Dave)
> 
> Tested in the cxl_for_7.3 branch.
> 
> 
> Alejandro Lucero (2):
>   cxl: Support Type2 cxl regs mapping
>   cxl: Support dpa without a mailbox
> 
>  drivers/cxl/core/core.h   |  2 ++
>  drivers/cxl/core/mbox.c   | 51 +----------------------------
>  drivers/cxl/core/memdev.c | 67 +++++++++++++++++++++++++++++++++++++++
>  drivers/cxl/core/pci.c    |  1 +
>  drivers/cxl/core/port.c   |  1 +
>  drivers/cxl/core/regs.c   |  1 +
>  drivers/cxl/cxlpci.h      | 12 -------
>  drivers/cxl/pci.c         |  1 +
>  include/cxl/cxl.h         |  2 ++
>  include/cxl/pci.h         | 22 +++++++++++++
>  10 files changed, 98 insertions(+), 62 deletions(-)
>  create mode 100644 include/cxl/pci.h
> 
> 
> base-commit: 9b1e70e8f9ec4b5c6ce7fa774a0023bb6894c686

Immutable branch created:
https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git/log/?h=for-7.3/cxl-type2-support

96ddf1af34f5 cxl: Support dpa without a mailbox
2c599da8231f cxl: Support Type2 cxl regs mapping

[PATCH v30 0/2] Type2 device basic support

[alejandro.lucero-palau]

From: Alejandro Lucero <alucerop@amd.com>

This series adds the last bits for allowing a CXL Type2 driver to obtain
a CXL region linked to the device HDM decoders committed by the BIOS.

For the sake of merging those changes and the driver using them, this
version only adds the changes without a client. A later series will
include sfc netdev driver as the client.

Changes from v29:

 - Only cxl core changes.

Changes from v28:

 - patch 1:
        fix doc (Ed Cree)
        fix error path (Sashiko)

 - patch 3:
        removing extra + char (sashiko)

 - path5:
        remove stray change (Ed Cree)

Changes from v27:

 - patch 1: make driver probe failing if error in efx_cxl_init (Dan)
 - patch 4: add unmapping if error after efx_cxl_init (Dave)
 - patch 4/5: move cxl_pio_initialised from patch 4 to patch 5 (Dave)

Tested in the cxl_for_7.3 branch.


Alejandro Lucero (2):
  cxl: Support Type2 cxl regs mapping
  cxl: Support dpa without a mailbox

 drivers/cxl/core/core.h   |  2 ++
 drivers/cxl/core/mbox.c   | 51 +----------------------------
 drivers/cxl/core/memdev.c | 67 +++++++++++++++++++++++++++++++++++++++
 drivers/cxl/core/pci.c    |  1 +
 drivers/cxl/core/port.c   |  1 +
 drivers/cxl/core/regs.c   |  1 +
 drivers/cxl/cxlpci.h      | 12 -------
 drivers/cxl/pci.c         |  1 +
 include/cxl/cxl.h         |  2 ++
 include/cxl/pci.h         | 22 +++++++++++++
 10 files changed, 98 insertions(+), 62 deletions(-)
 create mode 100644 include/cxl/pci.h


base-commit: 9b1e70e8f9ec4b5c6ce7fa774a0023bb6894c686
-- 
2.34.1

[PATCH v30 1/2] cxl: Support Type2 cxl regs mapping

[alejandro.lucero-palau]

From: Alejandro Lucero <alucerop@amd.com>

Export cxl core functions for a Type2 driver being able to discover and
map the device registers.

Signed-off-by: Alejandro Lucero <alucerop@amd.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
Acked-by: Edward Cree <ecree.xilinx@gmail.com>
---
 drivers/cxl/core/pci.c  |  1 +
 drivers/cxl/core/port.c |  1 +
 drivers/cxl/core/regs.c |  1 +
 drivers/cxl/cxlpci.h    | 12 ------------
 drivers/cxl/pci.c       |  1 +
 include/cxl/pci.h       | 22 ++++++++++++++++++++++
 6 files changed, 26 insertions(+), 12 deletions(-)
 create mode 100644 include/cxl/pci.h

diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index d1f487b3d809..2bcd683aa286 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -6,6 +6,7 @@
 #include <linux/delay.h>
 #include <linux/pci.h>
 #include <linux/pci-doe.h>
+#include <cxl/pci.h>
 #include <linux/aer.h>
 #include <cxlpci.h>
 #include <cxlmem.h>
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 1215ee4f4035..cb633e19151b 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -11,6 +11,7 @@
 #include <linux/idr.h>
 #include <linux/node.h>
 #include <cxl/einj.h>
+#include <cxl/pci.h>
 #include <cxlmem.h>
 #include <cxlpci.h>
 #include <cxl.h>
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index 93710cf4f0a6..20c2d9fbcfe7 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -4,6 +4,7 @@
 #include <linux/device.h>
 #include <linux/slab.h>
 #include <linux/pci.h>
+#include <cxl/pci.h>
 #include <cxlmem.h>
 #include <cxlpci.h>
 #include <pmu.h>
diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
index b826eb53cf7b..110ec9c44f09 100644
--- a/drivers/cxl/cxlpci.h
+++ b/drivers/cxl/cxlpci.h
@@ -13,16 +13,6 @@
  */
 #define CXL_PCI_DEFAULT_MAX_VECTORS 16
 
-/* Register Block Identifier (RBI) */
-enum cxl_regloc_type {
-	CXL_REGLOC_RBI_EMPTY = 0,
-	CXL_REGLOC_RBI_COMPONENT,
-	CXL_REGLOC_RBI_VIRT,
-	CXL_REGLOC_RBI_MEMDEV,
-	CXL_REGLOC_RBI_PMU,
-	CXL_REGLOC_RBI_TYPES
-};
-
 /*
  * Table Access DOE, CDAT Read Entry Response
  *
@@ -112,6 +102,4 @@ static inline void devm_cxl_port_ras_setup(struct cxl_port *port)
 }
 #endif
 
-int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
-		       struct cxl_register_map *map);
 #endif /* __CXL_PCI_H__ */
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 267c679b0b3c..bb892dbfdd6d 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -11,6 +11,7 @@
 #include <linux/pci.h>
 #include <linux/aer.h>
 #include <linux/io.h>
+#include <cxl/pci.h>
 #include <cxl/mailbox.h>
 #include "cxlmem.h"
 #include "cxlpci.h"
diff --git a/include/cxl/pci.h b/include/cxl/pci.h
new file mode 100644
index 000000000000..3e0000015871
--- /dev/null
+++ b/include/cxl/pci.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
+
+#ifndef __CXL_CXL_PCI_H__
+#define __CXL_CXL_PCI_H__
+
+/* Register Block Identifier (RBI) */
+enum cxl_regloc_type {
+	CXL_REGLOC_RBI_EMPTY = 0,
+	CXL_REGLOC_RBI_COMPONENT,
+	CXL_REGLOC_RBI_VIRT,
+	CXL_REGLOC_RBI_MEMDEV,
+	CXL_REGLOC_RBI_PMU,
+	CXL_REGLOC_RBI_TYPES
+};
+
+struct cxl_register_map;
+struct pci_dev;
+
+int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
+		       struct cxl_register_map *map);
+#endif
-- 
2.34.1

[PATCH v30 2/2] cxl: Support dpa without a mailbox

[alejandro.lucero-palau]

From: Alejandro Lucero <alucerop@amd.com>

Type3 relies on mailbox CXL_MBOX_OP_IDENTIFY command for initializing
memdev state params which end up being used for DPA initialization.

Allow a Type2 driver to initialize DPA simply by giving the size of its
volatile hardware partition.

Move related functions to memdev.

Signed-off-by: Alejandro Lucero <alucerop@amd.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Edward Cree <ecree.xilinx@gmail.com>
---
 drivers/cxl/core/core.h   |  2 ++
 drivers/cxl/core/mbox.c   | 51 +----------------------------
 drivers/cxl/core/memdev.c | 67 +++++++++++++++++++++++++++++++++++++++
 include/cxl/cxl.h         |  2 ++
 4 files changed, 72 insertions(+), 50 deletions(-)

diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
index 07555ae63859..f7cebb026552 100644
--- a/drivers/cxl/core/core.h
+++ b/drivers/cxl/core/core.h
@@ -101,6 +101,8 @@ void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
 struct dentry *cxl_debugfs_create_dir(const char *dir);
 int cxl_dpa_set_part(struct cxl_endpoint_decoder *cxled,
 		     enum cxl_partition_mode mode);
+struct cxl_memdev_state;
+int cxl_mem_get_partition_info(struct cxl_memdev_state *mds);
 int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, u64 size);
 int cxl_dpa_free(struct cxl_endpoint_decoder *cxled);
 resource_size_t cxl_dpa_size(struct cxl_endpoint_decoder *cxled);
diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
index 7c6c5b7450a5..97b1e61ad018 100644
--- a/drivers/cxl/core/mbox.c
+++ b/drivers/cxl/core/mbox.c
@@ -1152,7 +1152,7 @@ EXPORT_SYMBOL_NS_GPL(cxl_mem_get_event_records, "CXL");
  *
  * See CXL @8.2.9.5.2.1 Get Partition Info
  */
-static int cxl_mem_get_partition_info(struct cxl_memdev_state *mds)
+int cxl_mem_get_partition_info(struct cxl_memdev_state *mds)
 {
 	struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox;
 	struct cxl_mbox_get_partition_info pi;
@@ -1308,55 +1308,6 @@ int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd)
 	return -EBUSY;
 }
 
-static void add_part(struct cxl_dpa_info *info, u64 start, u64 size, enum cxl_partition_mode mode)
-{
-	int i = info->nr_partitions;
-
-	if (size == 0)
-		return;
-
-	info->part[i].range = (struct range) {
-		.start = start,
-		.end = start + size - 1,
-	};
-	info->part[i].mode = mode;
-	info->nr_partitions++;
-}
-
-int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
-{
-	struct cxl_dev_state *cxlds = &mds->cxlds;
-	struct device *dev = cxlds->dev;
-	int rc;
-
-	if (!cxlds->media_ready) {
-		info->size = 0;
-		return 0;
-	}
-
-	info->size = mds->total_bytes;
-
-	if (mds->partition_align_bytes == 0) {
-		add_part(info, 0, mds->volatile_only_bytes, CXL_PARTMODE_RAM);
-		add_part(info, mds->volatile_only_bytes,
-			 mds->persistent_only_bytes, CXL_PARTMODE_PMEM);
-		return 0;
-	}
-
-	rc = cxl_mem_get_partition_info(mds);
-	if (rc) {
-		dev_err(dev, "Failed to query partition information\n");
-		return rc;
-	}
-
-	add_part(info, 0, mds->active_volatile_bytes, CXL_PARTMODE_RAM);
-	add_part(info, mds->active_volatile_bytes, mds->active_persistent_bytes,
-		 CXL_PARTMODE_PMEM);
-
-	return 0;
-}
-EXPORT_SYMBOL_NS_GPL(cxl_mem_dpa_fetch, "CXL");
-
 int cxl_get_dirty_count(struct cxl_memdev_state *mds, u32 *count)
 {
 	struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox;
diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
index 33a3d2e7b13a..2e457b1ebc7d 100644
--- a/drivers/cxl/core/memdev.c
+++ b/drivers/cxl/core/memdev.c
@@ -594,6 +594,73 @@ bool is_cxl_memdev(const struct device *dev)
 }
 EXPORT_SYMBOL_NS_GPL(is_cxl_memdev, "CXL");
 
+static void add_part(struct cxl_dpa_info *info, u64 start, u64 size, enum cxl_partition_mode mode)
+{
+	int i = info->nr_partitions;
+
+	if (size == 0)
+		return;
+
+	info->part[i].range = (struct range) {
+		.start = start,
+		.end = start + size - 1,
+	};
+	info->part[i].mode = mode;
+	info->nr_partitions++;
+}
+
+int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info)
+{
+	struct cxl_dev_state *cxlds = &mds->cxlds;
+	struct device *dev = cxlds->dev;
+	int rc;
+
+	if (!cxlds->media_ready) {
+		info->size = 0;
+		return 0;
+	}
+
+	info->size = mds->total_bytes;
+
+	if (mds->partition_align_bytes == 0) {
+		add_part(info, 0, mds->volatile_only_bytes, CXL_PARTMODE_RAM);
+		add_part(info, mds->volatile_only_bytes,
+			 mds->persistent_only_bytes, CXL_PARTMODE_PMEM);
+		return 0;
+	}
+
+	rc = cxl_mem_get_partition_info(mds);
+	if (rc) {
+		dev_err(dev, "Failed to query partition information\n");
+		return rc;
+	}
+
+	add_part(info, 0, mds->active_volatile_bytes, CXL_PARTMODE_RAM);
+	add_part(info, mds->active_volatile_bytes, mds->active_persistent_bytes,
+		 CXL_PARTMODE_PMEM);
+
+	return 0;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_mem_dpa_fetch, "CXL");
+
+
+/**
+ * cxl_set_capacity: initialize dpa by a driver without a mailbox.
+ *
+ * @cxlds: pointer to cxl_dev_state
+ * @capacity: device volatile memory size
+ */
+int cxl_set_capacity(struct cxl_dev_state *cxlds, u64 capacity)
+{
+	struct cxl_dpa_info range_info = {
+		.size = capacity,
+	};
+
+	add_part(&range_info, 0, capacity, CXL_PARTMODE_RAM);
+	return cxl_dpa_setup(cxlds, &range_info);
+}
+EXPORT_SYMBOL_NS_GPL(cxl_set_capacity, "CXL");
+
 /**
  * set_exclusive_cxl_commands() - atomically disable user cxl commands
  * @mds: The device state to operate on
diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
index 016c74fb747c..802b143de83d 100644
--- a/include/cxl/cxl.h
+++ b/include/cxl/cxl.h
@@ -226,4 +226,6 @@ struct cxl_dev_state *_devm_cxl_dev_state_create(struct device *dev,
 
 struct cxl_memdev *devm_cxl_probe_mem(struct cxl_dev_state *cxlds,
 				      struct range *range);
+
+int cxl_set_capacity(struct cxl_dev_state *cxlds, u64 capacity);
 #endif /* __CXL_CXL_H__ */
-- 
2.34.1

Re: [PATCH v30 0/2] Type2 device basic support

[Dave Jiang]

On 6/29/26 11:37 AM, alejandro.lucero-palau@amd.com wrote:
> From: Alejandro Lucero <alucerop@amd.com>
> 
> This series adds the last bits for allowing a CXL Type2 driver to obtain
> a CXL region linked to the device HDM decoders committed by the BIOS.
> 
> For the sake of merging those changes and the driver using them, this
> version only adds the changes without a client. A later series will
> include sfc netdev driver as the client.
> 
> Changes from v29:
> 
>  - Only cxl core changes.
> 
> Changes from v28:
> 
>  - patch 1:
>         fix doc (Ed Cree)
>         fix error path (Sashiko)
> 
>  - patch 3:
>         removing extra + char (sashiko)
> 
>  - path5:
>         remove stray change (Ed Cree)
> 
> Changes from v27:
> 
>  - patch 1: make driver probe failing if error in efx_cxl_init (Dan)
>  - patch 4: add unmapping if error after efx_cxl_init (Dave)
>  - patch 4/5: move cxl_pio_initialised from patch 4 to patch 5 (Dave)
> 
> Tested in the cxl_for_7.3 branch.
> 
> 
> Alejandro Lucero (2):
>   cxl: Support Type2 cxl regs mapping
>   cxl: Support dpa without a mailbox
> 
>  drivers/cxl/core/core.h   |  2 ++
>  drivers/cxl/core/mbox.c   | 51 +----------------------------
>  drivers/cxl/core/memdev.c | 67 +++++++++++++++++++++++++++++++++++++++
>  drivers/cxl/core/pci.c    |  1 +
>  drivers/cxl/core/port.c   |  1 +
>  drivers/cxl/core/regs.c   |  1 +
>  drivers/cxl/cxlpci.h      | 12 -------
>  drivers/cxl/pci.c         |  1 +
>  include/cxl/cxl.h         |  2 ++
>  include/cxl/pci.h         | 22 +++++++++++++
>  10 files changed, 98 insertions(+), 62 deletions(-)
>  create mode 100644 include/cxl/pci.h
> 
> 
> base-commit: 9b1e70e8f9ec4b5c6ce7fa774a0023bb6894c686

Applied to cxl/next
96ddf1af34f5 cxl: Support dpa without a mailbox
2c599da8231f cxl: Support Type2 cxl regs mapping