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From: Dave Jiang <dave.jiang@intel.com>
To: Robert Richter <rrichter@amd.com>,
	Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Davidlohr Bueso <dave@stgolabs.net>
Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
	Gregory Price <gourry@gourry.net>,
	"Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>,
	Terry Bowman <terry.bowman@amd.com>
Subject: Re: [PATCH v3 05/18] cxl: Introduce parent_port_of() helper
Date: Thu, 20 Feb 2025 09:12:15 -0700	[thread overview]
Message-ID: <d5a62c06-9897-4967-8cac-8454b8f6b24b@intel.com> (raw)
In-Reply-To: <20250211095349.981096-6-rrichter@amd.com>



On 2/11/25 2:53 AM, Robert Richter wrote:
> Often a parent port must be determined. Introduce the parent_port_of()
> helper function for this.
> 
> Signed-off-by: Robert Richter <rrichter@amd.com>
> Reviewed-by: Gregory Price <gourry@gourry.net>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Tested-by: Gregory Price <gourry@gourry.net>

Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
>  drivers/cxl/core/port.c   | 15 +++++++++------
>  drivers/cxl/core/region.c | 11 ++---------
>  drivers/cxl/cxl.h         |  1 +
>  3 files changed, 12 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index f9501a16b390..d19930c009ce 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -606,17 +606,20 @@ struct cxl_port *to_cxl_port(const struct device *dev)
>  }
>  EXPORT_SYMBOL_NS_GPL(to_cxl_port, "CXL");
>  
> +struct cxl_port *parent_port_of(struct cxl_port *port)
> +{
> +	if (!port || !port->parent_dport)
> +		return NULL;
> +	return port->parent_dport->port;
> +}
> +EXPORT_SYMBOL_NS_GPL(parent_port_of, "CXL");
> +
>  static void unregister_port(void *_port)
>  {
>  	struct cxl_port *port = _port;
> -	struct cxl_port *parent;
> +	struct cxl_port *parent = parent_port_of(port);
>  	struct device *lock_dev;
>  
> -	if (is_cxl_root(port))
> -		parent = NULL;
> -	else
> -		parent = to_cxl_port(port->dev.parent);
> -
>  	/*
>  	 * CXL root port's and the first level of ports are unregistered
>  	 * under the platform firmware device lock, all other ports are
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 5d252dfae138..54afdb0fa61c 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -1734,13 +1734,6 @@ static int cmp_interleave_pos(const void *a, const void *b)
>  	return cxled_a->pos - cxled_b->pos;
>  }
>  
> -static struct cxl_port *next_port(struct cxl_port *port)
> -{
> -	if (!port->parent_dport)
> -		return NULL;
> -	return port->parent_dport->port;
> -}
> -
>  static int match_switch_decoder_by_range(struct device *dev,
>  					 const void *data)
>  {
> @@ -1767,7 +1760,7 @@ static int find_pos_and_ways(struct cxl_port *port, struct range *range,
>  	struct device *dev;
>  	int rc = -ENXIO;
>  
> -	parent = next_port(port);
> +	parent = parent_port_of(port);
>  	if (!parent)
>  		return rc;
>  
> @@ -1847,7 +1840,7 @@ static int cxl_calc_interleave_pos(struct cxl_endpoint_decoder *cxled)
>  	 */
>  
>  	/* Iterate from endpoint to root_port refining the position */
> -	for (iter = port; iter; iter = next_port(iter)) {
> +	for (iter = port; iter; iter = parent_port_of(iter)) {
>  		if (is_cxl_root(iter))
>  			break;
>  
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 6baec4ba9141..0d7aff8b97b3 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -721,6 +721,7 @@ static inline bool is_cxl_root(struct cxl_port *port)
>  int cxl_num_decoders_committed(struct cxl_port *port);
>  bool is_cxl_port(const struct device *dev);
>  struct cxl_port *to_cxl_port(const struct device *dev);
> +struct cxl_port *parent_port_of(struct cxl_port *port);
>  void cxl_port_commit_reap(struct cxl_decoder *cxld);
>  struct pci_bus;
>  int devm_cxl_register_pci_bus(struct device *host, struct device *uport_dev,


  reply	other threads:[~2025-02-20 16:12 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-11  9:53 [PATCH v3 00/18] cxl: Address translation support, part 1: Cleanups and refactoring Robert Richter
2025-02-11  9:53 ` [PATCH v3 01/18] cxl: Remove else after return Robert Richter
2025-02-11  9:53 ` [PATCH v3 02/18] cxl/pci: Moving code in cxl_hdm_decode_init() Robert Richter
2025-02-12 17:57   ` Jonathan Cameron
2025-02-20  1:03   ` Dave Jiang
2025-02-11  9:53 ` [PATCH v3 03/18] cxl/pci: cxl_hdm_decode_init: Move comment Robert Richter
2025-02-12 18:09   ` Jonathan Cameron
2025-02-13  0:35     ` Robert Richter
2025-02-14 15:49       ` Jonathan Cameron
2025-03-06  9:38         ` Robert Richter
2025-02-11  9:53 ` [PATCH v3 04/18] cxl/pci: Add comments to cxl_hdm_decode_init() Robert Richter
2025-02-14 15:51   ` Jonathan Cameron
2025-02-11  9:53 ` [PATCH v3 05/18] cxl: Introduce parent_port_of() helper Robert Richter
2025-02-20 16:12   ` Dave Jiang [this message]
2025-02-11  9:53 ` [PATCH v3 06/18] cxl/region: Rename function to cxl_find_decoder_early() Robert Richter
2025-02-14 15:58   ` Jonathan Cameron
2025-03-05 12:48     ` Robert Richter
2025-02-11  9:53 ` [PATCH v3 07/18] cxl/region: Avoid duplicate call of cxl_find_decoder_early() Robert Richter
2025-02-14 16:07   ` Jonathan Cameron
2025-03-06  9:16     ` Robert Richter
2025-02-11  9:53 ` [PATCH v3 08/18] cxl/region: Move find_cxl_root() to cxl_add_to_region() Robert Richter
2025-02-20 16:39   ` Dave Jiang
2025-02-11  9:53 ` [PATCH v3 09/18] cxl/region: Factor out code to find the root decoder Robert Richter
2025-02-20 16:48   ` Dave Jiang
2025-02-11  9:53 ` [PATCH v3 10/18] cxl/region: Factor out code to find a root decoder's region Robert Richter
2025-02-14 16:15   ` Jonathan Cameron
2025-02-20 16:50   ` Dave Jiang
2025-02-11  9:53 ` [PATCH v3 11/18] cxl/region: Split region registration into an initialization and adding part Robert Richter
2025-02-14 16:24   ` Jonathan Cameron
2025-02-11  9:53 ` [PATCH v3 12/18] cxl/region: Use iterator to find the root port in cxl_find_root_decoder() Robert Richter
2025-02-20 17:17   ` Dave Jiang
2025-02-11  9:53 ` [PATCH v3 13/18] cxl/region: Add function to find a port's switch decoder by range Robert Richter
2025-02-14 16:29   ` Jonathan Cameron
2025-02-20 17:23   ` Dave Jiang
2025-02-11  9:53 ` [PATCH v3 14/18] cxl/region: Unfold cxl_find_root_decoder() into cxl_endpoint_decoder_initialize() Robert Richter
2025-02-14 16:33   ` Jonathan Cameron
2025-03-06 16:18     ` Robert Richter
2025-02-11  9:53 ` [PATCH v3 15/18] cxl/region: Add a dev_warn() on registration failure Robert Richter
2025-02-14 16:35   ` Jonathan Cameron
2025-02-20 17:35     ` Dave Jiang
2025-02-11  9:53 ` [PATCH v3 16/18] cxl/region: Add a dev_err() on missing target list entries Robert Richter
2025-02-14 16:36   ` Jonathan Cameron
2025-02-20 17:44   ` Dave Jiang
2025-02-11  9:53 ` [PATCH v3 17/18] cxl: Add a dev_dbg() when a decoder was added to a port Robert Richter
2025-02-14 16:37   ` Jonathan Cameron
2025-02-20 17:45   ` Dave Jiang
2025-02-11  9:53 ` [PATCH v3 18/18] cxl/acpi: Unify CFMWS memory log messages with SRAT messages Robert Richter
2025-02-14 16:37   ` Jonathan Cameron
2025-02-20 17:46   ` Dave Jiang

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