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From: "Bowman, Terry" <terry.bowman@amd.com>
To: Lukas Wunner <lukas@wunner.de>
Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-pci@vger.kernel.org, nifan.cxl@gmail.com,
	ming4.li@intel.com, dave@stgolabs.net,
	jonathan.cameron@huawei.com, dave.jiang@intel.com,
	alison.schofield@intel.com, vishal.l.verma@intel.com,
	dan.j.williams@intel.com, bhelgaas@google.com,
	mahesh@linux.ibm.com, ira.weiny@intel.com, oohall@gmail.com,
	Benjamin.Cheatham@amd.com, rrichter@amd.com,
	nathan.fontenot@amd.com, Smita.KoralahalliChannabasappa@amd.com
Subject: Re: [PATCH v3 03/15] cxl/pci: Introduce PCIe helper functions pcie_is_cxl() and pcie_is_cxl_port()
Date: Thu, 14 Nov 2024 10:45:39 -0600	[thread overview]
Message-ID: <ffd740e5-235a-4b74-8bf9-91331b619a7f@amd.com> (raw)
In-Reply-To: <ZzYbHZvU_RFXZuk0@wunner.de>

Hi Lukas,

I added comments below.

On 11/14/2024 9:45 AM, Lukas Wunner wrote:
> On Wed, Nov 13, 2024 at 03:54:17PM -0600, Terry Bowman wrote:
>> --- a/drivers/pci/pci.c
>> +++ b/drivers/pci/pci.c
>> @@ -5038,6 +5038,20 @@ static u16 cxl_port_dvsec(struct pci_dev *dev)
>>  					 PCI_DVSEC_CXL_PORT);
>>  }
>>  
>> +bool pcie_is_cxl_port(struct pci_dev *dev)
>> +{
>> +	if (!pcie_is_cxl(dev))
>> +		return false;
>> +
>> +	if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
>> +	    (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) &&
>> +	    (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))
>> +		return false;
>> +
>> +	return cxl_port_dvsec(dev);
>> +}
>> +EXPORT_SYMBOL_GPL(pcie_is_cxl_port);
> This doesn't need to be exported because the only caller introduced
> in this series is in drivers/pci/pcie/aer.c (in patch 05/15), which
> is dependent on CONFIG_PCIEAER, which is bool not tristate.
Ok.
> The "!pcie_is_cxl(dev)" check at the top of the function is identical
> to the return value "cxl_port_dvsec(dev)".  This looks redundant.
> However one cannot call pci_pcie_type() without first checking
> pci_is_pcie().  So I'm wondering if the "!pcie_is_cxl(dev)" check
> is actually erroneous and supposed to be "!pci_is_pcie(dev)"?
> That would make more sense to me.

I see pcie_is_cxl(dev) is different than cxl_port_dvsec(dev).They check different DVSECs.[1] CXL flexbus DVSEC presence is cached in pci_dev::is_cxl and returned by pcie_is_cxl().
This is used for indicating CXL device.

cxl_port_dvsec(dev) returns boolean based on presence of CXL port DVSEC to 
indicate a CXL port device.

I don't believe they are redundant if you consider you can have a CXL device that 
is not a CXL port device. 

[1] - CXL 3.1, 8.1.1 Specification, PCIe Designated Vendor-Specific Extended Capability (DVSEC) ID Assignment
> Alternatively, just return true instead of "cxl_port_dvsec(dev)".
> That would probably be the simplest solution here.
>
>> --- a/include/linux/pci.h
>> +++ b/include/linux/pci.h
>> @@ -443,6 +443,7 @@ struct pci_dev {
>>  	unsigned int	is_hotplug_bridge:1;
>>  	unsigned int	shpc_managed:1;		/* SHPC owned by shpchp */
>>  	unsigned int	is_thunderbolt:1;	/* Thunderbolt controller */
>> +	unsigned int	is_cxl:1;               /* CXL alternate protocol */
> I suspect the audience consists mostly of CXL-unaware PCI developers,
> so spelling out Compute Express Link here (and omitting "alternate
> protocol" if it doesn't fit) might be more appropriate.
>
> Thanks,
>
> Lukas
Ok.

Regards,
Terry

  reply	other threads:[~2024-11-14 16:45 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-13 21:54 [PATCH v3 0/15] Enable CXL PCIe port protocol error handling and logging Terry Bowman
2024-11-13 21:54 ` [PATCH v3 01/15] PCI/AER: Introduce 'struct cxl_err_handlers' and add to 'struct pci_driver' Terry Bowman
2024-11-13 21:54 ` [PATCH v3 02/15] PCI/AER: Rename AER driver's interfaces to also indicate CXL PCIe port support Terry Bowman
2024-11-13 21:54 ` [PATCH v3 03/15] cxl/pci: Introduce PCIe helper functions pcie_is_cxl() and pcie_is_cxl_port() Terry Bowman
2024-11-14 15:45   ` Lukas Wunner
2024-11-14 16:45     ` Bowman, Terry [this message]
2024-11-14 16:52       ` Lukas Wunner
2024-11-14 17:07         ` Bowman, Terry
2024-11-15  8:47           ` Lukas Wunner
2024-11-15 13:54             ` Bowman, Terry
2024-11-17 17:02               ` Lukas Wunner
2024-11-19 12:20                 ` Bowman, Terry
2024-11-13 21:54 ` [PATCH v3 04/15] PCI/AER: Modify AER driver logging to report CXL or PCIe bus error type Terry Bowman
2024-11-13 21:54 ` [PATCH v3 05/15] PCI/AER: Add CXL PCIe port correctable error support in AER service driver Terry Bowman
2024-11-14 16:44   ` Lukas Wunner
2024-11-14 18:41     ` Bowman, Terry
2024-11-15  8:51       ` Lukas Wunner
2024-11-15 13:56         ` Bowman, Terry
2024-11-15 14:49       ` Li Ming
2024-11-15 19:46         ` Bowman, Terry
2024-11-17  7:38           ` Li Ming
2024-11-27 17:03   ` Jonathan Cameron
2024-11-27 20:29     ` Bowman, Terry
2024-11-13 21:54 ` [PATCH v3 06/15] PCI/AER: Change AER driver to read UCE fatal status for all CXL PCIe port devices Terry Bowman
2024-11-15  9:35   ` Lukas Wunner
2024-11-21 20:24     ` Bowman, Terry
2024-11-27 17:05       ` Jonathan Cameron
2024-11-27 20:53         ` Bowman, Terry
2024-11-13 21:54 ` [PATCH v3 07/15] PCI/AER: Add CXL PCIe port uncorrectable error recovery in AER service driver Terry Bowman
2024-11-18 10:37   ` Lukas Wunner
2024-11-19 12:23     ` Bowman, Terry
2024-11-13 21:54 ` [PATCH v3 08/15] cxl/pci: Map CXL PCIe root port and downstream switch port RAS registers Terry Bowman
2024-11-15 15:28   ` Li Ming
2024-11-15 19:33     ` Bowman, Terry
2024-11-16 14:49   ` kernel test robot
2024-11-17  7:45   ` Li Ming
2024-11-18  2:21     ` Li Ming
2024-11-19 12:28       ` Bowman, Terry
2024-11-13 21:54 ` [PATCH v3 09/15] cxl/pci: Map CXL PCIe upstream " Terry Bowman
2024-11-13 21:54 ` [PATCH v3 10/15] cxl/pci: Update RAS handler interfaces to also support CXL PCIe ports Terry Bowman
2024-11-13 21:54 ` [PATCH v3 11/15] cxl/pci: Change find_cxl_port() to non-static Terry Bowman
2024-11-13 21:54 ` [PATCH v3 12/15] cxl/pci: Add error handler for CXL PCIe port RAS errors Terry Bowman
2024-11-13 21:54 ` [PATCH v3 13/15] cxl/pci: Add trace logging " Terry Bowman
2024-11-13 21:54 ` [PATCH v3 14/15] cxl/pci: Add support to assign and clear pci_driver::cxl_err_handlers Terry Bowman
2024-11-13 21:54 ` [PATCH v3 15/15] PCI/AER: Enable internal errors for CXL upstream and downstream switch ports Terry Bowman
2024-11-18 11:54   ` Lukas Wunner
2024-11-21 22:25     ` Bowman, Terry
2024-11-21 22:32       ` Lukas Wunner

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