Re: [PATCH 2/2] arm64: dts: qcom: monaco-evk: Describe the PCIe M.2 Key E connector

Re: [PATCH 2/2] arm64: dts: qcom: monaco-evk: Describe the PCIe M.2 Key E connector

[Wei Deng]

Hi Konrad,

On Mon, 27 Jul 2026 16:43:50 +0200, Konrad Dybcio wrote:
> On 7/27/26 4:16 PM, Wei Deng wrote:
> > @@ -644,6 +701,12 @@ &pcie1_phy {
> >  &pcieport0 {
> >  	reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
> >  	wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
> > +
> > +	port {
> > +		pcieport0_ep: endpoint {
> > +			remote-endpoint = <&m2_e_pcie_ep>;
> > +		};
> > +	};
> 
> This should be defined in the SoC DTSI.
> 
> >  };
> >  
> >  &pcieport1 {
> > @@ -923,3 +986,13 @@ &usb_2_hsphy {
> >  
> >  	status = "okay";
> >  };
> > +
> > +&uart2 {
> > +	status = "okay";
> > +
> > +	port {
> > +		uart2_ep: endpoint {
> > +			remote-endpoint = <&m2_e_uart_ep>;
> > +		};
> > +	};
> 
> On a second thought, it would be logical to move this over there
> as well
> 
> Konrad

The concern I have with moving these to monaco.dtsi is that other
boards sharing the same DTSI (e.g. qcs8300-ride.dts) don't have an
M.2 connector. Adding port/endpoint nodes in the SoC DTSI would
create dangling endpoints on those boards.

The lemans-evk series followed the board-level approach (endpoint
defined in lemans-evk.dts) and was accepted by Bjorn. Would you
prefer a different approach for monaco, or is keeping it in the
EVK DTS acceptable here as well?

-- 
Best Regards,
Wei Deng

Re: [PATCH 2/2] arm64: dts: qcom: monaco-evk: Describe the PCIe M.2 Key E connector

[Konrad Dybcio]

On 7/28/26 5:39 AM, Wei Deng wrote:
> Hi Konrad,
> 
> On Mon, 27 Jul 2026 16:43:50 +0200, Konrad Dybcio wrote:
>> On 7/27/26 4:16 PM, Wei Deng wrote:
>>> @@ -644,6 +701,12 @@ &pcie1_phy {
>>>  &pcieport0 {
>>>  	reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
>>>  	wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
>>> +
>>> +	port {
>>> +		pcieport0_ep: endpoint {
>>> +			remote-endpoint = <&m2_e_pcie_ep>;
>>> +		};
>>> +	};

[...]

> The concern I have with moving these to monaco.dtsi is that other
> boards sharing the same DTSI (e.g. qcs8300-ride.dts) don't have an
> M.2 connector. Adding port/endpoint nodes in the SoC DTSI would
> create dangling endpoints on those boards.

Is that a problem?

Konrad

Re: [PATCH 2/2] arm64: dts: qcom: monaco-evk: Describe the PCIe M.2 Key E connector

[Wei Deng]

Hi Konrad,

On Tue, 28 Jul 2026 10:11:30 +0200, Konrad Dybcio wrote:
> On 7/28/26 5:39 AM, Wei Deng wrote:
> > The concern I have with moving these to monaco.dtsi is that other
> > boards sharing the same DTSI (e.g. qcs8300-ride.dts) don't have an
> > M.2 connector. Adding port/endpoint nodes in the SoC DTSI would
> > create dangling endpoints on those boards.
> 
> Is that a problem?
> 
> Konrad

Fair point. I will move the port/endpoint anchors to monaco.dtsi in v2.
I will also split the series into 3 patches to keep the SoC-level
changes separate from the board-level connector description.

-- 
Best Regards,
Wei Deng

Re: [PATCH 2/2] arm64: dts: qcom: monaco-evk: Describe the PCIe M.2 Key E connector

[Wei Deng]

On Wed, 29 Jul 2026 08:06:54 +0530, Wei Deng wrote:
> Fair point. I will move the port/endpoint anchors to monaco.dtsi in v2.

After testing v2 on qcs8300-ride-sx, BT init broke. qcs8300-ride-sx has a
soldered WCN6855 and no M.2 Key E connector, but the pending series [1]
uses of_graph_is_present() to detect whether an M.2 connector is present.
Since of_graph_is_present() only checks for a 'port' child node, the empty
anchors in monaco.dtsi caused hci_qca to incorrectly enter the M.2 pwrseq
path on all monaco boards.

v3 moves the port/endpoint nodes back to monaco-evk.dts. Please review.

[1] https://lore.kernel.org/all/20260720-monza-wireless-v5-1-69ec6743543c@oss.qualcomm.com/

-- 
Best Regards,
Wei Deng

Re: [PATCH 2/2] arm64: dts: qcom: monaco-evk: Describe the PCIe M.2 Key E connector

[Konrad Dybcio]

On 8/19/26 4:13 PM, Wei Deng wrote:
> On Wed, 29 Jul 2026 08:06:54 +0530, Wei Deng wrote:
>> Fair point. I will move the port/endpoint anchors to monaco.dtsi in v2.
> 
> After testing v2 on qcs8300-ride-sx, BT init broke. qcs8300-ride-sx has a
> soldered WCN6855 and no M.2 Key E connector, but the pending series [1]
> uses of_graph_is_present() to detect whether an M.2 connector is present.
> Since of_graph_is_present() only checks for a 'port' child node, the empty
> anchors in monaco.dtsi caused hci_qca to incorrectly enter the M.2 pwrseq
> path on all monaco boards.
> 
> v3 moves the port/endpoint nodes back to monaco-evk.dts. Please review.
> 
> [1] https://lore.kernel.org/all/20260720-monza-wireless-v5-1-69ec6743543c@oss.qualcomm.com/

The series should test of_graph_get_remote_endpoint() instead

Konrad

[PATCH 0/2] arm64: dts: qcom: Describe the PCIe M.2 Key E connector for Monaco EVK

[Wei Deng]

Add DT support for the PCIe M.2 Mechanical Key E connector on the
Monaco EVK, following the same pattern as the lemans-evk
series (already applied by Bjorn, commits 67f06acf/a6d4bb0a).

Patch 1 adds 'compatible = "pciclass,0604"' to the pcieport0 node in
monaco.dtsi, required for downstream DT nodes to be matched to PCI
devices.

Patch 2 describes the connector-3 node in monaco-evk.dts, links it
with PCIe 0 Root Port and UART2 via graph port/endpoint, adds the
vreg_wcn_3p3/vreg_dcin_12v regulators, and adds the serial1 = &uart2
alias for BT serdev enumeration.

This series is based on next-20260726.

---
Wei Deng (2):
      arm64: dts: qcom: monaco: Add compatible to the PCIe Root Port
      arm64: dts: qcom: monaco-evk: Describe the PCIe M.2 Key E connector

 arch/arm64/boot/dts/qcom/monaco-evk.dts | 73 +++++++++++++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/monaco.dtsi    |  1 +
 2 files changed, 74 insertions(+)
---
base-commit: c5e32e86ca02b003f86e095d379b38148999293d
change-id: 20260727-b4-monaco-evk-m2-v1-dd56eb997378

Best regards,
-- 
Wei Deng <wei.deng@oss.qualcomm.com>

[PATCH 2/2] arm64: dts: qcom: monaco-evk: Describe the PCIe M.2 Key E connector

[Wei Deng]

The monaco EVK has a PCIe M.2 Mechanical Key E connector to connect
wireless connectivity cards over PCIe and UART interfaces. Hence,
describe the connector node and link it with the PCIe 0 Root Port and
UART2 nodes through graph port/endpoint.

The M.2 Key E connector is powered by a 3.3V fixed regulator
(vreg_wcn_3p3) which is sourced from the board's 12V DC input rail
(vreg_dcin_12v). Both regulators are always-on and are required by the
pcie-m2-e-connector binding.

Also add the serial1 = &uart2 alias, which is required for the
Bluetooth serdev device to be enumerated on the UART2 interface.

Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/monaco-evk.dts | 73 +++++++++++++++++++++++++++++++++
 1 file changed, 73 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts
index 9d17ef7d2caf..87ec0be89ccf 100644
--- a/arch/arm64/boot/dts/qcom/monaco-evk.dts
+++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts
@@ -21,6 +21,7 @@ aliases {
 		ethernet0 = &ethernet0;
 		i2c1 = &i2c1;
 		serial0 = &uart7;
+		serial1 = &uart2;
 		serial2 = &uart6;
 	};
 
@@ -47,6 +48,38 @@ usb2_con_hs_ep: endpoint {
 		};
 	};
 
+	connector-3 {
+		compatible = "pcie-m2-e-connector";
+		vpcie3v3-supply = <&vreg_wcn_3p3>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				m2_e_pcie_ep: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&pcieport0_ep>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				m2_e_uart_ep: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&uart2_ep>;
+				};
+			};
+		};
+	};
+
 	dmic: audio-codec-0 {
 		compatible = "dmic-codec";
 		#sound-dai-cells = <0>;
@@ -91,6 +124,30 @@ usb2_vbus: regulator-usb2-vbus {
 		enable-active-high;
 	};
 
+	vreg_dcin_12v: regulator-dcin-12v {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_DCIN_12V";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vreg_wcn_3p3: regulator-wcn-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_WCN_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		vin-supply = <&vreg_dcin_12v>;
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
 	sound {
 		compatible = "qcom,qcs8275-sndcard";
 		model = "MONACO-EVK";
@@ -644,6 +701,12 @@ &pcie1_phy {
 &pcieport0 {
 	reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
 	wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+
+	port {
+		pcieport0_ep: endpoint {
+			remote-endpoint = <&m2_e_pcie_ep>;
+		};
+	};
 };
 
 &pcieport1 {
@@ -923,3 +986,13 @@ &usb_2_hsphy {
 
 	status = "okay";
 };
+
+&uart2 {
+	status = "okay";
+
+	port {
+		uart2_ep: endpoint {
+			remote-endpoint = <&m2_e_uart_ep>;
+		};
+	};
+};

-- 
2.34.1

Re: [PATCH 2/2] arm64: dts: qcom: monaco-evk: Describe the PCIe M.2 Key E connector

[Dmitry Baryshkov]

On Mon, Jul 27, 2026 at 07:46:32PM +0530, Wei Deng wrote:
> The monaco EVK has a PCIe M.2 Mechanical Key E connector to connect
> wireless connectivity cards over PCIe and UART interfaces. Hence,
> describe the connector node and link it with the PCIe 0 Root Port and
> UART2 nodes through graph port/endpoint.
> 
> The M.2 Key E connector is powered by a 3.3V fixed regulator
> (vreg_wcn_3p3) which is sourced from the board's 12V DC input rail
> (vreg_dcin_12v). Both regulators are always-on and are required by the
> pcie-m2-e-connector binding.
> 
> Also add the serial1 = &uart2 alias, which is required for the
> Bluetooth serdev device to be enumerated on the UART2 interface.
> 
> Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/monaco-evk.dts | 73 +++++++++++++++++++++++++++++++++
>  1 file changed, 73 insertions(+)
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>


-- 
With best wishes
Dmitry

Re: [PATCH 2/2] arm64: dts: qcom: monaco-evk: Describe the PCIe M.2 Key E connector

[Konrad Dybcio]

On 7/27/26 4:16 PM, Wei Deng wrote:
> The monaco EVK has a PCIe M.2 Mechanical Key E connector to connect
> wireless connectivity cards over PCIe and UART interfaces. Hence,
> describe the connector node and link it with the PCIe 0 Root Port and
> UART2 nodes through graph port/endpoint.
> 
> The M.2 Key E connector is powered by a 3.3V fixed regulator
> (vreg_wcn_3p3) which is sourced from the board's 12V DC input rail
> (vreg_dcin_12v). Both regulators are always-on and are required by the
> pcie-m2-e-connector binding.
> 
> Also add the serial1 = &uart2 alias, which is required for the
> Bluetooth serdev device to be enumerated on the UART2 interface.
> 
> Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
> ---

[...]

> @@ -644,6 +701,12 @@ &pcie1_phy {
>  &pcieport0 {
>  	reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
>  	wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
> +
> +	port {
> +		pcieport0_ep: endpoint {
> +			remote-endpoint = <&m2_e_pcie_ep>;
> +		};
> +	};

This should be defined in the SoC DTSI.

>  };
>  
>  &pcieport1 {
> @@ -923,3 +986,13 @@ &usb_2_hsphy {
>  
>  	status = "okay";
>  };
> +
> +&uart2 {
> +	status = "okay";
> +
> +	port {
> +		uart2_ep: endpoint {
> +			remote-endpoint = <&m2_e_uart_ep>;
> +		};
> +	};

On a second thought, it would be logical to move this over there
as well

Konrad