* [PATCH v4 1/7] dt-bindings: soc: renesas: Add various SolidRun RZ/G2 based boards
2026-09-02 11:50 [PATCH v4 0/7] arm64: dts: renesas: Add various SolidRun RZ/G2 based boards Josua Mayer
@ 2026-09-02 11:50 ` Josua Mayer
2026-09-02 11:50 ` [PATCH v4 2/7] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow input-enable pinconf Josua Mayer
` (6 subsequent siblings)
7 siblings, 0 replies; 18+ messages in thread
From: Josua Mayer @ 2026-09-02 11:50 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Benjamin Bara, Linus Walleij,
Lad Prabhakar
Cc: Jon Nettleton, Mikhail Anikin, Yazan Shhady, linux-renesas-soc,
devicetree, linux-kernel, linux-usb, linux-gpio, Josua Mayer,
Conor Dooley
Add bindings for various SolidRun boards and System on Module built
around Renesas RZ/G2 family of SoCs:
- RZ/G2L SoM [1]
- RZ/V2L SoM [2]
(shares PCB with G2L and has very similar programming model)
- RZ/G2LC SoM [3]
- RZ/G2UL SoM [4]
(shares PCB with G2LC but programming model differs largely)
- HummingBoard IIoT [5] (RZ/G2L, RZ/V2L, RZ/G2LC)
- HummingBoard Pro [6] (RZ/G2L, RZ/V2L)
- HummingBoard Base (Ripple) [7] (RZ/G2L, RZ/V2L, RZ/G2LC, RZ/G2UL)
[1] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2l-som/
[2] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-v2l-som/
[3] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2lc-som/
[4] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2ul-som/
[5] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2l-iot-sbc/
[6] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2l-sbc/
[7] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2lc-base/
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
.../devicetree/bindings/soc/renesas/renesas.yaml | 37 ++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
index eeef34e3d7d07..1673005a3d930 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
@@ -508,6 +508,14 @@ properties:
- renesas,r9a07g043u12 # RZ/G2UL Type-2
- const: renesas,r9a07g043
+ - description: SolidRun RZ/G2UL based boards
+ items:
+ - enum:
+ - solidrun,rzg2ul-hummingboard-ripple # SolidRun RZ/G2UL HummingBoard Ripple
+ - const: solidrun,rzg2ul-sr-som
+ - const: renesas,r9a07g043u12 # RZ/G2UL Type-2
+ - const: renesas,r9a07g043
+
- description: RZ/G2{L,LC} (R9A07G044)
items:
- enum:
@@ -519,6 +527,25 @@ properties:
- renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L
- const: renesas,r9a07g044
+ - description: SolidRun RZ/G2L based boards
+ items:
+ - enum:
+ - solidrun,rzg2l-hummingboard-iiot # SolidRun RZ/G2L HummingBoard IIoT
+ - solidrun,rzg2l-hummingboard-pro # SolidRun RZ/G2L HummingBoard Pro
+ - solidrun,rzg2l-hummingboard-ripple # SolidRun RZ/G2L HummingBoard Ripple
+ - const: solidrun,rzg2l-sr-som
+ - const: renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L
+ - const: renesas,r9a07g044
+
+ - description: SolidRun RZ/G2LC based boards
+ items:
+ - enum:
+ - solidrun,rzg2lc-hummingboard-iiot # SolidRun RZ/G2LC HummingBoard IIoT
+ - solidrun,rzg2lc-hummingboard-ripple # SolidRun RZ/G2LC HummingBoard Ripple
+ - const: solidrun,rzg2lc-sr-som
+ - const: renesas,r9a07g044c2 # Dual Cortex-A55 RZ/G2LC
+ - const: renesas,r9a07g044
+
- items:
- enum:
# MYIR Remi Pi SBC (MYB-YG2LX-REMI)
@@ -535,6 +562,16 @@ properties:
- renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L
- const: renesas,r9a07g054
+ - description: SolidRun RZ/V2L based boards
+ items:
+ - enum:
+ - solidrun,rzv2l-hummingboard-iiot # SolidRun RZ/V2L HummingBoard IIoT
+ - solidrun,rzv2l-hummingboard-pro # SolidRun RZ/V2L HummingBoard Pro
+ - solidrun,rzv2l-hummingboard-ripple # SolidRun RZ/V2L HummingBoard Ripple
+ - const: solidrun,rzv2l-sr-som
+ - const: renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L
+ - const: renesas,r9a07g054
+
- description: RZ/G3S (R9A08G045)
items:
- enum:
--
2.51.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v4 2/7] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow input-enable pinconf
2026-09-02 11:50 [PATCH v4 0/7] arm64: dts: renesas: Add various SolidRun RZ/G2 based boards Josua Mayer
2026-09-02 11:50 ` [PATCH v4 1/7] dt-bindings: soc: " Josua Mayer
@ 2026-09-02 11:50 ` Josua Mayer
2026-09-02 12:58 ` Linus Walleij
2026-09-02 11:50 ` [PATCH v4 3/7] dt-bindings: usb: cypress,hx3: make peer-hub property optional Josua Mayer
` (5 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Josua Mayer @ 2026-09-02 11:50 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Benjamin Bara, Linus Walleij,
Lad Prabhakar
Cc: Jon Nettleton, Mikhail Anikin, Yazan Shhady, linux-renesas-soc,
devicetree, linux-kernel, linux-usb, linux-gpio, Josua Mayer
The list of allowed pinconf properties already includes input-enable,
but has omitted input-disable.
Both refer to the same hardware property, setting and clearing input-enable.
Add input-disable to the list.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index fb1fe1ea759fc..5089be4770ae5 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -135,6 +135,7 @@ additionalProperties:
gpios: true
input: true
input-enable: true
+ input-disable: true
output-enable: true
output-high: true
output-low: true
--
2.51.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v4 2/7] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow input-enable pinconf
2026-09-02 11:50 ` [PATCH v4 2/7] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow input-enable pinconf Josua Mayer
@ 2026-09-02 12:58 ` Linus Walleij
2026-09-03 9:23 ` Josua Mayer
0 siblings, 1 reply; 18+ messages in thread
From: Linus Walleij @ 2026-09-02 12:58 UTC (permalink / raw)
To: Josua Mayer
Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Benjamin Bara, Lad Prabhakar,
Jon Nettleton, Mikhail Anikin, Yazan Shhady, linux-renesas-soc,
devicetree, linux-kernel, linux-usb, linux-gpio
Hi Joshua,
thanks for your patch!
On Wed, Sep 2, 2026 at 1:50 PM Josua Mayer <josua@solid-run.com> wrote:
> The list of allowed pinconf properties already includes input-enable,
> but has omitted input-disable.
>
> Both refer to the same hardware property, setting and clearing input-enable.
>
> Add input-disable to the list.
>
> Signed-off-by: Josua Mayer <josua@solid-run.com>
(...)
> + input-disable: true
The Subject of this patch is "Allow input-enable pinconf".
But what you are doing is allowing input-disable.
With the subject fixed:
Reviewed-by: Linus Walleij <linusw@kernel.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v4 2/7] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow input-enable pinconf
2026-09-02 12:58 ` Linus Walleij
@ 2026-09-03 9:23 ` Josua Mayer
2026-09-04 10:12 ` Geert Uytterhoeven
0 siblings, 1 reply; 18+ messages in thread
From: Josua Mayer @ 2026-09-03 9:23 UTC (permalink / raw)
To: Linus Walleij
Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Benjamin Bara, Lad Prabhakar,
Jon Nettleton, Mikhail Anikin, Yazan Shhady,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org,
linux-gpio@vger.kernel.org
Am 02.09.26 um 14:58 schrieb Linus Walleij:
> Hi Joshua,
>
> thanks for your patch!
>
> On Wed, Sep 2, 2026 at 1:50 PM Josua Mayer <josua@solid-run.com> wrote:
>
>> The list of allowed pinconf properties already includes input-enable,
>> but has omitted input-disable.
>>
>> Both refer to the same hardware property, setting and clearing input-enable.
>>
>> Add input-disable to the list.
>>
>> Signed-off-by: Josua Mayer <josua@solid-run.com>
> (...)
>> + input-disable: true
> The Subject of this patch is "Allow input-enable pinconf".
>
> But what you are doing is allowing input-disable.
>
> With the subject fixed:
> Reviewed-by: Linus Walleij <linusw@kernel.org>
Thanks!
I'll fix the subject ... !
("dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow input-disable pinconf")
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v4 2/7] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow input-enable pinconf
2026-09-03 9:23 ` Josua Mayer
@ 2026-09-04 10:12 ` Geert Uytterhoeven
2026-09-04 11:14 ` Josua Mayer
0 siblings, 1 reply; 18+ messages in thread
From: Geert Uytterhoeven @ 2026-09-04 10:12 UTC (permalink / raw)
To: Josua Mayer
Cc: Linus Walleij, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Benjamin Bara, Lad Prabhakar,
Jon Nettleton, Mikhail Anikin, Yazan Shhady,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org,
linux-gpio@vger.kernel.org
Hi Joshua,
On Thu, 3 Sept 2026 at 11:23, Josua Mayer <josua@solid-run.com> wrote:
> Am 02.09.26 um 14:58 schrieb Linus Walleij:
> > On Wed, Sep 2, 2026 at 1:50 PM Josua Mayer <josua@solid-run.com> wrote:
> >> The list of allowed pinconf properties already includes input-enable,
> >> but has omitted input-disable.
> >>
> >> Both refer to the same hardware property, setting and clearing input-enable.
> >>
> >> Add input-disable to the list.
> >>
> >> Signed-off-by: Josua Mayer <josua@solid-run.com>
> > (...)
> >> + input-disable: true
> > The Subject of this patch is "Allow input-enable pinconf".
> >
> > But what you are doing is allowing input-disable.
> >
> > With the subject fixed:
> > Reviewed-by: Linus Walleij <linusw@kernel.org>
> Thanks!
> I'll fix the subject ... !
>
> ("dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow input-disable pinconf")
No need to resend, I will fix this while applying
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-pinctrl for v7.4.
I will also add "output-disable", which is missing, too.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v4 2/7] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow input-enable pinconf
2026-09-04 10:12 ` Geert Uytterhoeven
@ 2026-09-04 11:14 ` Josua Mayer
2026-09-04 11:16 ` Geert Uytterhoeven
0 siblings, 1 reply; 18+ messages in thread
From: Josua Mayer @ 2026-09-04 11:14 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Linus Walleij, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Benjamin Bara, Lad Prabhakar,
Jon Nettleton, Mikhail Anikin, Yazan Shhady,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org,
linux-gpio@vger.kernel.org
Hi Geert,
Am 04.09.26 um 12:12 schrieb Geert Uytterhoeven:
> Hi Joshua,
>
> On Thu, 3 Sept 2026 at 11:23, Josua Mayer <josua@solid-run.com> wrote:
>> Am 02.09.26 um 14:58 schrieb Linus Walleij:
>>> On Wed, Sep 2, 2026 at 1:50 PM Josua Mayer <josua@solid-run.com> wrote:
>>>> The list of allowed pinconf properties already includes input-enable,
>>>> but has omitted input-disable.
>>>>
>>>> Both refer to the same hardware property, setting and clearing input-enable.
>>>>
>>>> Add input-disable to the list.
>>>>
>>>> Signed-off-by: Josua Mayer <josua@solid-run.com>
>>> (...)
>>>> + input-disable: true
>>> The Subject of this patch is "Allow input-enable pinconf".
>>>
>>> But what you are doing is allowing input-disable.
>>>
>>> With the subject fixed:
>>> Reviewed-by: Linus Walleij <linusw@kernel.org>
>> Thanks!
>> I'll fix the subject ... !
>>
>> ("dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow input-disable pinconf")
> No need to resend, I will fix this while applying
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> i.e. will queue in renesas-pinctrl for v7.4.
>
> I will also add "output-disable", which is missing, too.
Thanks!
However I am ready to send v8. If I drop it my series will fail dtbs_check.
Is it okay if I do resend it, and/or should I wait and cherry-pick your
version
so that it is easily dropped while applying without conflict?
Or drop it and live with failing dtbs_check?
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v4 2/7] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow input-enable pinconf
2026-09-04 11:14 ` Josua Mayer
@ 2026-09-04 11:16 ` Geert Uytterhoeven
2026-09-04 11:33 ` Josua Mayer
0 siblings, 1 reply; 18+ messages in thread
From: Geert Uytterhoeven @ 2026-09-04 11:16 UTC (permalink / raw)
To: Josua Mayer
Cc: Linus Walleij, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Benjamin Bara, Lad Prabhakar,
Jon Nettleton, Mikhail Anikin, Yazan Shhady,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org,
linux-gpio@vger.kernel.org
Hi Josua,
On Fri, 4 Sept 2026 at 13:14, Josua Mayer <josua@solid-run.com> wrote:
> Am 04.09.26 um 12:12 schrieb Geert Uytterhoeven:
> > On Thu, 3 Sept 2026 at 11:23, Josua Mayer <josua@solid-run.com> wrote:
> >> Am 02.09.26 um 14:58 schrieb Linus Walleij:
> >>> On Wed, Sep 2, 2026 at 1:50 PM Josua Mayer <josua@solid-run.com> wrote:
> >>>> The list of allowed pinconf properties already includes input-enable,
> >>>> but has omitted input-disable.
> >>>>
> >>>> Both refer to the same hardware property, setting and clearing input-enable.
> >>>>
> >>>> Add input-disable to the list.
> >>>>
> >>>> Signed-off-by: Josua Mayer <josua@solid-run.com>
> >>> (...)
> >>>> + input-disable: true
> >>> The Subject of this patch is "Allow input-enable pinconf".
> >>>
> >>> But what you are doing is allowing input-disable.
> >>>
> >>> With the subject fixed:
> >>> Reviewed-by: Linus Walleij <linusw@kernel.org>
> >> Thanks!
> >> I'll fix the subject ... !
> >>
> >> ("dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow input-disable pinconf")
> > No need to resend, I will fix this while applying
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > i.e. will queue in renesas-pinctrl for v7.4.
> >
> > I will also add "output-disable", which is missing, too.
>
> Thanks!
>
> However I am ready to send v8. If I drop it my series will fail dtbs_check.
> Is it okay if I do resend it, and/or should I wait and cherry-pick your
> version
> so that it is easily dropped while applying without conflict?
>
> Or drop it and live with failing dtbs_check?
If you're ready, then please send v8 (and add "output-disable").
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v4 2/7] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow input-enable pinconf
2026-09-04 11:16 ` Geert Uytterhoeven
@ 2026-09-04 11:33 ` Josua Mayer
0 siblings, 0 replies; 18+ messages in thread
From: Josua Mayer @ 2026-09-04 11:33 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Linus Walleij, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Benjamin Bara, Lad Prabhakar,
Jon Nettleton, Mikhail Anikin, Yazan Shhady,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org,
linux-gpio@vger.kernel.org
Am 04.09.26 um 13:16 schrieb Geert Uytterhoeven:
> Hi Josua,
>
> On Fri, 4 Sept 2026 at 13:14, Josua Mayer <josua@solid-run.com> wrote:
>> Am 04.09.26 um 12:12 schrieb Geert Uytterhoeven:
>>> On Thu, 3 Sept 2026 at 11:23, Josua Mayer <josua@solid-run.com> wrote:
>>>> Am 02.09.26 um 14:58 schrieb Linus Walleij:
>>>>> On Wed, Sep 2, 2026 at 1:50 PM Josua Mayer <josua@solid-run.com> wrote:
>>>>>> The list of allowed pinconf properties already includes input-enable,
>>>>>> but has omitted input-disable.
>>>>>>
>>>>>> Both refer to the same hardware property, setting and clearing input-enable.
>>>>>>
>>>>>> Add input-disable to the list.
>>>>>>
>>>>>> Signed-off-by: Josua Mayer <josua@solid-run.com>
>>>>> (...)
>>>>>> + input-disable: true
>>>>> The Subject of this patch is "Allow input-enable pinconf".
>>>>>
>>>>> But what you are doing is allowing input-disable.
>>>>>
>>>>> With the subject fixed:
>>>>> Reviewed-by: Linus Walleij <linusw@kernel.org>
>>>> Thanks!
>>>> I'll fix the subject ... !
>>>>
>>>> ("dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow input-disable pinconf")
>>> No need to resend, I will fix this while applying
>>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>> i.e. will queue in renesas-pinctrl for v7.4.
>>>
>>> I will also add "output-disable", which is missing, too.
>> Thanks!
>>
>> However I am ready to send v8. If I drop it my series will fail dtbs_check.
>> Is it okay if I do resend it, and/or should I wait and cherry-pick your
>> version
>> so that it is easily dropped while applying without conflict?
>>
>> Or drop it and live with failing dtbs_check?
> If you're ready, then please send v8 (and add "output-disable").
> Thanks!
Ack. I will send it within the hour.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v4 3/7] dt-bindings: usb: cypress,hx3: make peer-hub property optional
2026-09-02 11:50 [PATCH v4 0/7] arm64: dts: renesas: Add various SolidRun RZ/G2 based boards Josua Mayer
2026-09-02 11:50 ` [PATCH v4 1/7] dt-bindings: soc: " Josua Mayer
2026-09-02 11:50 ` [PATCH v4 2/7] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow input-enable pinconf Josua Mayer
@ 2026-09-02 11:50 ` Josua Mayer
2026-09-02 11:50 ` [PATCH v4 4/7] arm64: dts: renesas: add support for solidrun rzg2l som and hb-iiot evb Josua Mayer
` (4 subsequent siblings)
7 siblings, 0 replies; 18+ messages in thread
From: Josua Mayer @ 2026-09-02 11:50 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Benjamin Bara, Linus Walleij,
Lad Prabhakar
Cc: Jon Nettleton, Mikhail Anikin, Yazan Shhady, linux-renesas-soc,
devicetree, linux-kernel, linux-usb, linux-gpio, Josua Mayer,
Krzysztof Kozlowski
Cypress HX3 Hubs are combined USB-2.0 and USB-3.0 devices, and should be
described by one node per speed and linked by peer-hub property.
It is however possible to install this Hub to a USB-2.0-only host, in
which case the USB-3.0 peer has no place in device-tree.
Remove peer-hub from required properties.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
Documentation/devicetree/bindings/usb/cypress,hx3.yaml | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/usb/cypress,hx3.yaml b/Documentation/devicetree/bindings/usb/cypress,hx3.yaml
index d6eac1213228d..aca2fe796240f 100644
--- a/Documentation/devicetree/bindings/usb/cypress,hx3.yaml
+++ b/Documentation/devicetree/bindings/usb/cypress,hx3.yaml
@@ -53,7 +53,6 @@ properties:
required:
- compatible
- reg
- - peer-hub
- vdd-supply
- vdd2-supply
--
2.51.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v4 4/7] arm64: dts: renesas: add support for solidrun rzg2l som and hb-iiot evb
2026-09-02 11:50 [PATCH v4 0/7] arm64: dts: renesas: Add various SolidRun RZ/G2 based boards Josua Mayer
` (2 preceding siblings ...)
2026-09-02 11:50 ` [PATCH v4 3/7] dt-bindings: usb: cypress,hx3: make peer-hub property optional Josua Mayer
@ 2026-09-02 11:50 ` Josua Mayer
2026-09-02 11:50 ` [PATCH v4 5/7] arm64: dts: renesas: add support for solidrun rzv2l " Josua Mayer
` (3 subsequent siblings)
7 siblings, 0 replies; 18+ messages in thread
From: Josua Mayer @ 2026-09-02 11:50 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Benjamin Bara, Linus Walleij,
Lad Prabhakar
Cc: Jon Nettleton, Mikhail Anikin, Yazan Shhady, linux-renesas-soc,
devicetree, linux-kernel, linux-usb, linux-gpio, Josua Mayer
Add support for the SolidRun RZ/G2L SoM [1] on Hummingboard IIoT [2].
The SoM features:
- 2x 1Gbps Ethernet with PHY
- eMMC
- 1/2GB DDR
- WiFi + Bluetooth
- SDHI Mux switching between eMMC and Carrier Board
The HummingBoard IIoT features:
- 3x USB-2.0 Type A connector
- 2x 1Gbps RJ45 Ethernet
- USB Type-C Console Port
- microSD connector
- RTC with backup battery
- RGB Status LED
- 1x M.2 B-Key connector with USB-2.0 + SIM card holder
- 1x DSI Display Connector
- GPIO header
- 2x RS232/RS485 ports (configurable)
- 2x CAN
Descriptions for eMMC, microSD and RS485 are provided as overlays due to
their dependency on configurable mux states.
[1] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2l-som/
[2] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2l-iot-sbc/
Link: https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2l-som/
Link: https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2l-iot-sbc/
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/renesas/Makefile | 13 +
.../dts/renesas/r9a07g044l2-hummingboard-iiot.dts | 16 +
.../renesas/rzg2l-hummingboard-iiot-common.dtsi | 564 +++++++++++++++++++++
.../renesas/rzg2l-hummingboard-iiot-microsd.dtso | 26 +
.../renesas/rzg2l-hummingboard-iiot-rs485-a.dtso | 17 +
.../renesas/rzg2l-hummingboard-iiot-rs485-b.dtso | 17 +
.../boot/dts/renesas/rzg2l-hummingboard-iiot.dtsi | 49 ++
arch/arm64/boot/dts/renesas/rzg2l-sr-som-emmc.dtso | 44 ++
arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi | 460 +++++++++++++++++
9 files changed, 1206 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 8bf155badd111..e2af196e18bf6 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -170,6 +170,19 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtbo
r9a07g044c2-smarc-cru-csi-ov5645-dtbs := r9a07g044c2-smarc.dtb r9a07g044c2-smarc-cru-csi-ov5645.dtbo
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-sr-som-emmc.dtbo
+r9a07g044l2-hummingboard-iiot-emmc-dtbs := r9a07g044l2-hummingboard-iiot.dtb rzg2l-sr-som-emmc.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-emmc.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-microsd.dtbo
+r9a07g044l2-hummingboard-iiot-microsd-dtbs := r9a07g044l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-microsd.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-microsd.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-rs485-a.dtbo
+r9a07g044l2-hummingboard-iiot-rs485-a-dtbs := r9a07g044l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-rs485-a.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-rs485-b.dtbo
+r9a07g044l2-hummingboard-iiot-rs485-b-dtbs := r9a07g044l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-b.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-rs485-b.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-remi-pi.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtbo
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-hummingboard-iiot.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-hummingboard-iiot.dts
new file mode 100644
index 0000000000000..eba4f423c8f05
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-hummingboard-iiot.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+/dts-v1/;
+
+#include "r9a07g044l2.dtsi"
+#include "rzg2l-sr-som.dtsi"
+#include "rzg2l-hummingboard-iiot.dtsi"
+
+/ {
+ compatible = "solidrun,rzg2l-hummingboard-iiot", "solidrun,rzg2l-sr-som",
+ "renesas,r9a07g044l2", "renesas,r9a07g044";
+ model = "SolidRun RZ/G2L HummingBoard IIoT";
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-common.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-common.dtsi
new file mode 100644
index 0000000000000..30b9cde57f046
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-common.dtsi
@@ -0,0 +1,564 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+/ {
+ /* power for M.2 B-Key connector (J6) */
+ regulator-m2-b {
+ compatible = "regulator-fixed";
+ regulator-name = "m2-b";
+ gpios = <&tca6416_u20 5 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ enable-active-high;
+ };
+
+ /* power for M.2 M-Key connector (J4) */
+ regulator-m2-m {
+ compatible = "regulator-fixed";
+ regulator-name = "m2-m";
+ gpios = <&tca6416_u20 6 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ enable-active-high;
+ };
+
+ /* power for USB-A J27 behind USB Hub Port 3 */
+ regulator-vbus-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus2";
+ regulator-always-on;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ gpios = <&tca6416_u20 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ /* power for USB-A J27 behind USB Hub Port 4 */
+ regulator-vbus-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus3";
+ regulator-always-on;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ gpios = <&tca6416_u20 13 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ aliases {
+ gpio1 = &tca6408_u48;
+ gpio2 = &tca6408_u37;
+ gpio3 = &tca6416_u20;
+ gpio4 = &tca6416_u21;
+ i2c3 = &i2c_exp;
+ i2c4 = &i2c_csi;
+ i2c5 = &i2c_dsi;
+ i2c6 = &i2c_lvds;
+ rtc0 = &carrier_rtc;
+ rtc1 = &pmic;
+ serial3 = &scif3;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ wakeup-event {
+ interrupts-extended = <&tca6416_u21 11 IRQ_TYPE_EDGE_FALLING>;
+ label = "m2-m-wakeup";
+ wakeup-source;
+ linux,code = <KEY_WAKEUP>;
+ };
+ };
+
+ can_mux: mux-controller-1 {
+ compatible = "gpio-mux";
+ /* default J9-55/57/59/61 to on-board transceivers */
+ idle-state = <0>;
+ #mux-control-cells = <0>;
+ /*
+ * Mux routes CAN bus signals between SoM connector pins,
+ * expansion connector (J22) and on-board transceivers using
+ * two GPIO:
+ * - IO3: 0 = on-board transceivers, 1 = expansion connector
+ * - IO4: 0 = J9-55/57/59/61, 1 = J7-12/16 & J9-54/56
+ */
+ mux-gpios = <&tca6416_u20 3 GPIO_ACTIVE_HIGH>,
+ <&tca6416_u20 4 GPIO_ACTIVE_HIGH>;
+ };
+
+ spi_mux: mux-controller-2 {
+ compatible = "gpio-mux";
+ /* default on-board */
+ idle-state = <0>;
+ /*
+ * Mux switches spi bus between on-board tpm
+ * and expansion connector (J22).
+ */
+ mux-gpios = <&tca6416_u21 0 GPIO_ACTIVE_HIGH>;
+ #mux-control-cells = <0>;
+ };
+
+ scif1_scif3_b2b_mux: mux-controller-3 {
+ compatible = "gpio-mux";
+ /* default on-board */
+ idle-state = <0>;
+ #mux-control-cells = <0>;
+ /*
+ * Mux switches both scif1 and scif3 tx/rx between expansion
+ * connector (J22) and on-board rs232/rs485 transceivers
+ * using one GPIO: 0 = on-board, 1 = connector.
+ */
+ mux-gpios = <&tca6416_u20 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ scif1_rs_232_485_mux: mux-controller-4 {
+ compatible = "gpio-mux";
+ /* default rs232 */
+ idle-state = <0>;
+ #mux-control-cells = <0>;
+ /*
+ * Mux switches scif1 tx/rx between rs232 and rs485
+ * transceivers. using one GPIO: 0 = rs232, 1 = rs485.
+ */
+ mux-gpios = <&tca6416_u20 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ scif3_rs_232_485_mux: mux-controller-5 {
+ compatible = "gpio-mux";
+ /* default rs232 */
+ idle-state = <0>;
+ #mux-control-cells = <0>;
+ /*
+ * Mux switches scif3 tx/rx between rs232 and rs485
+ * transceivers. using one GPIO: 0 = rs232, 1 = rs485.
+ */
+ mux-gpios = <&tca6416_u20 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ v_1_2: regulator-1-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v2";
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microvolt = <1200000>;
+ };
+
+ v_3_3: regulator-3-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ };
+
+ reg_dsi_panel: regulator-dsi-panel {
+ compatible = "regulator-fixed";
+ regulator-name = "dsi-panel";
+ gpios = <&tca6416_u20 15 GPIO_ACTIVE_HIGH>;
+ regulator-max-microvolt = <11200000>;
+ regulator-min-microvolt = <11200000>;
+ enable-active-high;
+ };
+
+ vmmc: regulator-mmc {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmc";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ startup-delay-us = <250>;
+ vin-supply = <&v_3_3>;
+ gpios = <&pinctrl RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ /* power for USB-A J5003 */
+ vbus1: regulator-vbus-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus1";
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ gpios = <&tca6416_u20 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ rfkill-m2-b-gnss {
+ compatible = "rfkill-gpio";
+ /* rfkill-gpio inverts internally */
+ shutdown-gpios = <&tca6416_u20 10 GPIO_ACTIVE_LOW>;
+ label = "m2-b gnss";
+ radio-type = "gps";
+ };
+
+ rfkill-m2-b-wwan {
+ compatible = "rfkill-gpio";
+ /* rfkill-gpio inverts internally */
+ shutdown-gpios = <&tca6416_u20 9 GPIO_ACTIVE_HIGH>;
+ label = "m2-b radio";
+ radio-type = "wwan";
+ };
+};
+
+&ehci1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hub_2_0: hub@1 {
+ compatible = "usb4b4,6502", "usb4b4,6506";
+ reg = <1>;
+ reset-gpios = <&tca6416_u20 11 GPIO_ACTIVE_LOW>;
+ vdd2-supply = <&v_3_3>;
+ vdd-supply = <&v_1_2>;
+ };
+};
+
+&i2c0 {
+ /* highest i2c clock supported by all peripherals is 400kHz */
+
+ tca6416_u20: gpio@20 {
+ compatible = "ti,tcal6416";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-line-names = "TCA_INT/EXT_UART", "TCA_UARTA_232/485",
+ "TCA_UARTB_232/485", "TCA_INT/EXT_CAN",
+ "TCA_NXP/REN", "TCA_M.2B_3V3_EN",
+ "TCA_M.2M_3V3_EN", "TCA_M.2M_RESET#",
+ "TCA_M.2B_RESET#", "TCA_M.2B_W_DIS#",
+ "TCA_M.2B_GPS_EN#", "TCA_USB-HUB_RST#",
+ "TCA_USB_HUB3_PWR_EN", "TCA_USB_HUB4_PWR_EN",
+ "TCA_USB1_PWR_EN", "TCA_VIDEO_PWR_EN";
+
+ m2-b-reset-hog {
+ gpios = <8 GPIO_ACTIVE_LOW>;
+ gpio-hog;
+ line-name = "m2-b-reset";
+ output-low;
+ };
+
+ m2-m-reset-hog {
+ gpios = <7 GPIO_ACTIVE_LOW>;
+ gpio-hog;
+ line-name = "m2-m-reset";
+ /*
+ * M.2 Key-M connector only supports PCI,
+ * but RZ/G2L(C) has no pci controller.
+ * Keep any card in reset.
+ */
+ output-high;
+ };
+ };
+
+ tca6416_u21: gpio@21 {
+ compatible = "ti,tcal6416";
+ reg = <0x21>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-line-names = "TCA_SPI_TPM/EXT", "TCA_TPM_RST#",
+ "TCA_I2C_RST", "TCA_RS232_SHTD#",
+ "TCA_LCD_I2C_RST", "TCA_DIG_OUT1",
+ "TCA_bDIG_IN1", "TCA_SENS_INT",
+ "TCA_ALERT#", "TCA_TPM_PIRQ#",
+ "TCA_RTC_INT", "TCA_M.2M_WAKW_ON_LAN",
+ "TCA_M.2M_CLKREQ#", "TCA_LVDS_INT#",
+ "", "TCA_POE_AT";
+ /*
+ * Level interrupts are typical for gpio expander but not supported on rz/g2l
+ * gpios. However since TCAL6416 latches interrupts and clears only on reading
+ * port register, falling edge trigger doesn't lose events.
+ */
+ interrupts-extended = <&pinctrl RZG2L_GPIO(4, 0) IRQ_TYPE_EDGE_FALLING>;
+
+ lcd-i2c-reset-hog {
+ gpios = <4 (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>;
+ line-name = "lcd-i2c-reset";
+ output-low;
+ /*
+ * reset shared between U37 and U48, to be
+ * supported once gpio-pca953x switches to
+ * reset framework.
+ */
+ gpio-hog;
+ };
+
+ lvds-irq-hog {
+ gpios = <13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ gpio-hog;
+ input;
+ line-name = "lvds-irq";
+ };
+
+ m2-m-clkreq-hog {
+ gpios = <12 GPIO_ACTIVE_LOW>;
+ gpio-hog;
+ input;
+ line-name = "m2-m-clkreq";
+ };
+
+ rs232_shutdown: rs232-shutdown-hog {
+ gpios = <3 GPIO_ACTIVE_LOW>;
+ gpio-hog;
+ line-name = "rs232-shutdown";
+ output-low;
+ };
+
+ sensor-irq-hog {
+ gpios = <7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ gpio-hog;
+ input;
+ line-name = "sensor-irq";
+ };
+
+ tpm-irq-hog {
+ gpios = <9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ gpio-hog;
+ input;
+ line-name = "tpm-irq";
+ };
+ };
+
+ led-controller@30 {
+ compatible = "ti,lp5562";
+ reg = <0x30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* use internal clock, could use external generated by rtc */
+ clock-mode = /bits/ 8 <1>;
+
+ multi-led@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ color = <LED_COLOR_ID_RGB>;
+ label = "D7";
+
+ led@0 {
+ reg = <0x0>;
+ color = <LED_COLOR_ID_RED>;
+ led-cur = /bits/ 8 <0x32>;
+ max-cur = /bits/ 8 <0x64>;
+ };
+
+ led@1 {
+ reg = <0x1>;
+ color = <LED_COLOR_ID_GREEN>;
+ led-cur = /bits/ 8 <0x19>;
+ max-cur = /bits/ 8 <0x32>;
+ };
+
+ led@2 {
+ reg = <0x2>;
+ color = <LED_COLOR_ID_BLUE>;
+ led-cur = /bits/ 8 <0x19>;
+ max-cur = /bits/ 8 <0x32>;
+ };
+ };
+
+ led@3 {
+ reg = <0x3>;
+ chan-name = "D8";
+ color = <LED_COLOR_ID_GREEN>;
+ label = "D8";
+ led-cur = /bits/ 8 <0x19>;
+ max-cur = /bits/ 8 <0x64>;
+ };
+ };
+
+ light-sensor@44 {
+ compatible = "isil,isl29023";
+ reg = <0x44>;
+ /* IRQ shared between accelerometer, light-sensor and Tamper input (J5007) */
+ interrupts-extended = <&tca6416_u21 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ accelerometer@53 {
+ compatible = "adi,adxl345";
+ reg = <0x53>;
+ interrupts-extended = <&tca6416_u21 7 IRQ_TYPE_LEVEL_LOW>;
+ /* IRQ shared between accelerometer, light-sensor and Tamper input (J5007) */
+ interrupt-names = "INT1";
+ };
+
+ carrier_eeprom: eeprom@57 {
+ compatible = "atmel,24c02";
+ reg = <0x57>;
+ pagesize = <8>;
+ };
+
+ carrier_rtc: rtc@69 {
+ compatible = "abracon,ab1805";
+ reg = <0x69>;
+ /*
+ * AM1805 RTC used on this board has only nTIRQ pins wired,
+ * which is for countdown timer irqs only.
+ * Driver does not support this, disable for now.
+ *
+ * interrupts-extended = <&tca6416_u21 10 IRQ_TYPE_LEVEL_LOW>;
+ */
+ abracon,tc-diode = "schottky";
+ abracon,tc-resistor = <3>;
+ };
+};
+
+&i2c1 {
+ /* highest i2c clock supported by all peripherals is 400kHz */
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /*
+ * This reset is open drain with HW 10k pull-up resistor,
+ * but reset core does not support GPIO_OPEN_DRAIN flag.
+ * The pull-up and GPIO voltages match, push-pull is safe.
+ */
+ reset-gpios = <&tca6416_u21 2 GPIO_ACTIVE_LOW>;
+
+ /* channel 0 routed to expansion connector (J22) */
+ i2c_exp: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ /* channel 1 routed to mipi-csi connector (J23) */
+ i2c_csi: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ /* channel 2 routed to mipi-dsi connector (J25) */
+ i2c_dsi: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6408_u48: gpio@21 {
+ compatible = "ti,tca6408";
+ reg = <0x21>;
+ #gpio-cells = <2>;
+ gpio-line-names = "CAM_RST#", "DSI_RESET",
+ "DSI_STBYB", "DSI_PWM_BL",
+ "DSI_L/R", "DSI_U/D",
+ "DSI_CTP_/RST", "CAM_TRIG";
+ /*
+ * reset shared between U37 and U48, to be
+ * supported once gpio-pca953x switches to
+ * reset framework.
+ *
+ * reset-gpios = <&tca6416_u21 4
+ * (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>;
+ */
+ gpio-controller;
+ };
+ };
+
+ /* channel 3 routed to lvds connector (J24) */
+ i2c_lvds: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6408_u37: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-line-names = "SELB", "LVDS_RESET",
+ "LVDS_STBYB", "LVDS_PWM_BL",
+ "LVDS_L/R", "LVDS_U/D",
+ "LVDS_CTP_/RST", "";
+ /*
+ * reset shared between U37 and U48, to be
+ * supported once gpio-pca953x switches to
+ * reset framework.
+ *
+ * reset-gpios = <&tca6416_u21 4
+ * (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>;
+ */
+ gpio-controller;
+ };
+ };
+ };
+};
+
+&phy0 {
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* LED_0 pin */
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "keep";
+ function = LED_FUNCTION_LAN;
+ };
+ };
+};
+
+&pinctrl {
+ /* UARTA */
+ scif1_pins: scif1 {
+ pinmux = <RZG2L_PORT_PINMUX(40, 1, 1)>, /* SCIF1_RXD */
+ <RZG2L_PORT_PINMUX(40, 0, 1)>; /* SCIF1_TXD */
+ };
+
+ /* UARTB */
+ scif3_pins: scif3 {
+ pinmux = <RZG2L_PORT_PINMUX(0, 1, 5)>, /* SCIF3_RXD */
+ <RZG2L_PORT_PINMUX(0, 0, 5)>; /* SCIF3_TXD */
+ };
+};
+
+&scif1 {
+ pinctrl-0 = <&scif1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&scif3 {
+ pinctrl-0 = <&scif3_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&spi1 {
+ /* native cs does not support cs persistence required for tpm */
+ cs-gpios = <&pinctrl RZG2L_GPIO(44, 3) GPIO_ACTIVE_LOW>;
+ num-cs = <1>;
+ pinctrl-0 = <&spi1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ spi1_muxed: spi@0 {
+ compatible = "spi-mux";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mux-controls = <&spi_mux>;
+ /* mux bandwidth is 2GHz, soc max. spi clock is P0/2 = 50MHz */
+ spi-max-frequency = <50000000>;
+
+ tpm@0 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <0>;
+ interrupts-extended = <&tca6416_u21 9 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&tca6416_u21 1 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+ spi-max-frequency = <43000000>;
+ };
+ };
+};
+
+&ohci0 {
+ dr_mode = "host";
+};
+
+&usb2_phy0 {
+ vbus-supply = <&vbus1>;
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-microsd.dtso b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-microsd.dtso
new file mode 100644
index 0000000000000..c86d46956f823
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-microsd.dtso
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+* Device Tree Overlay for the RZ/G2L(C) Solidrun SOM SD
+*
+* Copyright (C) 2024 SolidRun Ltd.
+*/
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+&sdhi0 {
+ bus-width = <4>;
+ full-pwr-cycle;
+ mux-states = <&sdhi0_mux 1>;
+ pinctrl-0 = <&sdhi0_4bit_pins>, <&sdhi0_cd_pins>;
+ pinctrl-1 = <&sdhi0_4bit_uhs_pins>, <&sdhi0_cd_pins>;
+ pinctrl-names = "default", "state_uhs";
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ vmmc-supply = <&vmmc>;
+ vqmmc-supply = <®_pmic_ldo1>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-a.dtso b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-a.dtso
new file mode 100644
index 0000000000000..4bcb22d518f05
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-a.dtso
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ *
+ * Overlay for enabling HummingBoard IIoT on-board RS485 Port A on connector J5004.
+ *
+ * Because Renesas uart driver does not support rs485,
+ * users must manually toggle P41_1 between RX & TX.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&scif1_rs_232_485_mux {
+ /* select rs485 */
+ idle-state = <1>;
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-b.dtso b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-b.dtso
new file mode 100644
index 0000000000000..6f460b3e0b256
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-b.dtso
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ *
+ * Overlay for enabling HummingBoard IIoT on-board RS485 Port B on connector J5004.
+ *
+ * Because Renesas uart driver does not support rs485,
+ * users must manually toggle P41_0 between RX & TX.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&scif3_rs_232_485_mux {
+ /* select rs485 */
+ idle-state = <1>;
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot.dtsi
new file mode 100644
index 0000000000000..22f066079e69a
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot.dtsi
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+#include "rzg2l-hummingboard-iiot-common.dtsi"
+
+&canfd {
+ pinctrl-names = "default";
+ pinctrl-0 = <&can0_pins>, <&can1_pins>;
+ status = "okay";
+
+ channel0 {
+ status = "okay";
+ };
+
+ channel1 {
+ status = "okay";
+ };
+};
+
+&phy1 {
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* LED_0 pin */
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
+};
+
+&pinctrl {
+ /* CANA */
+ can0_pins: can0 {
+ pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* CAN0_TX */
+ <RZG2L_PORT_PINMUX(11, 0, 2)>; /* CAN0_RX */
+ };
+
+ /* CANB */
+ can1_pins: can1 {
+ pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* CAN1_TX */
+ <RZG2L_PORT_PINMUX(13, 0, 2)>; /* CAN1_RX */
+ };
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-sr-som-emmc.dtso b/arch/arm64/boot/dts/renesas/rzg2l-sr-som-emmc.dtso
new file mode 100644
index 0000000000000..263a36994b03c
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-sr-som-emmc.dtso
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+* Device Tree Overlay for the RZ/G2L(C) Solidrun SOM eMMC
+*
+* Copyright (C) 2024 SolidRun Ltd.
+*/
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+®_pmic_ldo1 {
+ /*
+ * This ldo can switch mmc host controller io voltage between
+ * 1.8V and 3.3V. The eMMC IO voltage however is supplied from
+ * reg_pmic_buck3 which is fixed at 1.8V.
+ * Lower this ldo maximum voltage to 1.8V to prevent setting 3.3V.
+ */
+ regulator-max-microvolt = <1800000>;
+};
+
+&sdhi0 {
+ /*
+ * Host controller and eMMC have separate io voltage regulators:
+ * reg_pmic_ldo1 (1.8V/3.3V); reg_pmic_buck3 (1.8V only).
+ * Link to the switchable regulator ensuring that it gets configured.
+ */
+ vqmmc-supply = <®_pmic_ldo1>;
+ bus-width = <8>;
+ cap-mmc-hw-reset;
+ mmc-hs200-1_8v;
+ mux-states = <&sdhi0_mux 0>;
+ non-removable;
+ no-sdio;
+ pinctrl-0 = <&sdhi0_8bit_uhs_pins>, <&sdhi0_rst_pins>;
+ pinctrl-1 = <&sdhi0_8bit_uhs_pins>, <&sdhi0_rst_pins>;
+ pinctrl-names = "default", "state_uhs";
+ vmmc-supply = <®_pmic_buck4>;
+ /* emmc io voltage is hard-wired for 1.8V, disable sd modes */
+ no-sd;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi
new file mode 100644
index 0000000000000..5ae3ce8d6825a
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi
@@ -0,0 +1,460 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L Solidrun SoM
+ *
+ * Copyright 2023 SolidRun Ltd.
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+/ {
+ aliases {
+ ethernet0 = ð0;
+ ethernet1 = ð1;
+ gpio0 = &pinctrl;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c3;
+ mmc0 = &sdhi0;
+ mmc1 = &sdhi1;
+ rtc0 = &pmic;
+ serial0 = &scif0;
+ serial1 = &scif1;
+ serial2 = &scif2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ sdhi0_mux: mux-controller-0 {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+ #mux-state-cells = <1>;
+ /*
+ * Mux switches SD0_DATA[0-3], SD0_CMD & SD0_CLK between
+ * on-SoM eMMC and board-to-board connector using one gpio:
+ * Low = connector, High = eMMC.
+ * Define active-low for logical mux state 0 = eMMC, 1 = connector.
+ */
+ mux-gpios = <&pinctrl RZG2L_GPIO(22, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ clk_pmic_32k: pmic-32k-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ reg_pmic_buck1: regulator-pmic-buck1 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-buck1";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1100000>;
+ regulator-min-microvolt = <1100000>;
+ };
+
+ reg_pmic_buck3: regulator-pmic-buck3 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-buck3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ };
+
+ reg_pmic_buck4: regulator-pmic-buck4 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-buck4";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ };
+
+ reg_pmic_ldo1: regulator-pmic-ldo1 {
+ compatible = "regulator-gpio";
+ regulator-name = "pmic-ldo1";
+ gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ states = <3300000 1>, <1800000 0>;
+ };
+
+ reg_pmic_ldo2: regulator-pmic-ldo2 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-ldo2";
+ /*
+ * This ldo can switch mmc host controller io voltage between
+ * 1.8V and 3.3V by assembly option of pull-up / pull-dow.
+ * Default assembly is 3.3V.
+ */
+ regulator-min-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ mmp_reserved: linux,multimedia@68000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x68000000 0x0 0x8000000>;
+ reusable;
+ };
+
+ global_cma: linux,cma@58000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x58000000 0x0 0x10000000>;
+ reusable;
+ linux,cma-default;
+ };
+ };
+
+ sdhi1_pwrseq: sdhi1-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pinctrl RZG2L_GPIO(23, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ /* 32.768kHz crystal */
+ x2: x2-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ memory@40000000 {
+ reg = <0x0 0x40000000 0x0 0x40000000>;
+ device_type = "memory";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+ð0 {
+ phy-handle = <&phy0>;
+ pinctrl-0 = <ð0_pins>;
+ pinctrl-names = "default";
+ /*
+ * ravb driver does not configure mac internal delays for RZ/G2L(C),
+ * instead delays are added by the MxL86110 phy driver.
+ */
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ /* Level interrupts are typical for phy but not supported on rz/g2l gpios. */
+ interrupts-extended = <&pinctrl RZG2L_GPIO(27, 0) IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+ð1 {
+ phy-handle = <&phy1>;
+ pinctrl-0 = <ð1_pins>;
+ pinctrl-names = "default";
+ /*
+ * ravb driver does not configure mac internal delays for RZ/G2L(C),
+ * instead delays are added by the MxL86110 phy driver.
+ */
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ phy1: ethernet-phy@4 {
+ reg = <4>;
+ /* Level interrupts are typical for phy but not supported on rz/g2l gpios. */
+ interrupts-extended = <&pinctrl RZG2L_GPIO(42, 4) IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <24000000>;
+};
+
+&gpu {
+ mali-supply = <®_pmic_buck1>;
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c01";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ pmic: pmic@12 {
+ compatible = "renesas,raa215300";
+ reg = <0x12>, <0x6f>;
+ reg-names = "main", "rtc";
+ clocks = <&x2>;
+ clock-names = "xin";
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ostm1 {
+ status = "okay";
+};
+
+&ostm2 {
+ status = "okay";
+};
+
+&phyrst {
+ status = "okay";
+};
+
+&pinctrl {
+ eth0_pins: eth0 {
+ pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
+ <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
+ <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
+ <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
+ <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
+ <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
+ <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
+ <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
+ <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
+ <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
+ <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
+ <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
+ <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
+ <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
+ <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
+ };
+
+ eth1_pins: eth1 {
+ pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
+ <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
+ <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
+ <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
+ <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
+ <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
+ <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
+ <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
+ <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
+ <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
+ <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
+ <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
+ <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
+ <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
+ <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
+ };
+
+ i2c0_pins: i2c0 {
+ input-enable;
+ pins = "RIIC0_SDA", "RIIC0_SCL";
+ };
+
+ i2c1_pins: i2c1 {
+ input-enable;
+ pins = "RIIC1_SDA", "RIIC1_SCL";
+ };
+
+ i2c3_pins: i2c3 {
+ pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* RIIC3_SDA */
+ <RZG2L_PORT_PINMUX(18, 1, 3)>; /* RIIC3_SCL */
+ };
+
+ qspi0_pins: qspi0 {
+ pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3",
+ "QSPI0_SPCLK", "QSPI0_SSL";
+ power-source = <1800>;
+ };
+
+ scif0_pins: scif0 {
+ pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* SCIF0_TXD */
+ <RZG2L_PORT_PINMUX(38, 1, 1)>; /* SCIF0_RXD */
+ };
+
+ scif2_pins: scif2 {
+ pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* SCIF2_TXD */
+ <RZG2L_PORT_PINMUX(48, 1, 1)>, /* SCIF2_RXD */
+ <RZG2L_PORT_PINMUX(48, 3, 1)>, /* SCIF2_CTS# */
+ <RZG2L_PORT_PINMUX(48, 4, 1)>; /* SCIF2_RTS# */
+ };
+
+ sdhi0_4bit_pins: sdhi0-4bit {
+ sd0_ctrl_dat03 {
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
+ "SD0_CLK", "SD0_CMD";
+ power-source = <3300>;
+ };
+
+ /*
+ * Pins 4-7 are hard-wired to eMMC with 1.8V IO voltage,
+ * with all pins sharing a single voltage domain.
+ *
+ * These pins are fixed-function lacking independently configurable
+ * pull-up, pull-down or output-disable.
+ *
+ * While unused, disable the input buffers to avoid sampling the still
+ * physically connected but unused eMMC lines.
+ * For output direction rely on correct controller bus-width configuration
+ * to avoid over-voltage to eMMC e.g. when operating at 3.3V for a 4-bit microSD.
+ */
+ sd0_dat47 {
+ input-disable;
+ pins = "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
+ };
+ };
+
+ sdhi0_4bit_uhs_pins: sdhi0-4bit-uhs {
+ sd0_ctrl_dat03 {
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
+ "SD0_CLK", "SD0_CMD";
+ power-source = <1800>;
+ };
+
+ /*
+ * Pins 4-7 are hard-wired to eMMC with 1.8V IO voltage,
+ * with all pins sharing a single voltage domain.
+ *
+ * These pins are fixed-function lacking independently configurable
+ * pull-up, pull-down or output-disable.
+ *
+ * While unused, disable the input buffers to avoid sampling the still
+ * physically connected but unused eMMC lines.
+ * For output direction rely on correct controller bus-width configuration
+ * to avoid over-voltage to eMMC e.g. when operating at 3.3V for a 4-bit microSD.
+ */
+ sd0_dat47 {
+ input-disable;
+ pins = "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
+ };
+ };
+
+ sdhi0_8bit_uhs_pins: sdhi0-8bit-uhs {
+ input-enable;
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
+ "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7",
+ "SD0_CLK", "SD0_CMD";
+ power-source = <1800>;
+ };
+
+ sdhi0_cd_pins: sdhi0-cd {
+ pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
+ };
+
+ /* SD0_RST is only routed to eMMC which uses fixed 1.8V IO voltage */
+ sdhi0_rst_pins: sdhi0-rst {
+ pins = "SD0_RST#";
+ power-source = <1800>;
+ };
+
+ sdhi1_pins: sdhi1 {
+ pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3",
+ "SD1_CLK", "SD1_CMD";
+ power-source = <3300>;
+ };
+
+ spi1_pins: spi1 {
+ pinmux = <RZG2L_PORT_PINMUX(44, 2, 1)>, /* RSPI1_MISO */
+ <RZG2L_PORT_PINMUX(44, 1, 1)>, /* RSPI1_MOSI# */
+ <RZG2L_PORT_PINMUX(44, 0, 1)>;
+ };
+
+ spi1_cs_pins: spi1-cs {
+ pinmux = <RZG2L_PORT_PINMUX(44, 3, 1)>; /* RSPI1_SSL */
+ };
+};
+
+&sbc {
+ pinctrl-0 = <&qspi0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ flash@0 {
+ compatible = "winbond,w25q80bl", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ };
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+ status = "okay";
+};
+
+/* WiFi */
+&sdhi1 {
+ /* Murata 1MW max rate is 50MHz */
+ max-frequency = <50000000>;
+ bus-width = <4>;
+ cap-sdio-irq;
+ mmc-pwrseq = <&sdhi1_pwrseq>;
+ non-removable;
+ no-1-8-v;
+ no-sd;
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-names = "default";
+ vmmc-supply = <®_pmic_buck4>;
+ /*
+ * Host controller IO voltage is provided from reg_pmic_ldo2,
+ * WiFi module IO voltage from reg_pmic_buck4.
+ * Neither is configurable at run-time so either can be set here.
+ */
+ vqmmc-supply = <®_pmic_ldo2>;
+ status = "okay";
+};
+
+&usb2_phy0 {
+ vbus-supply = <&usb0_vbus_otg>;
+ status = "okay";
+};
+
+&usb2_phy1 {
+ status = "okay";
+};
+
+&wdt0 {
+ status = "okay";
+};
--
2.51.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v4 5/7] arm64: dts: renesas: add support for solidrun rzv2l som and hb-iiot evb
2026-09-02 11:50 [PATCH v4 0/7] arm64: dts: renesas: Add various SolidRun RZ/G2 based boards Josua Mayer
` (3 preceding siblings ...)
2026-09-02 11:50 ` [PATCH v4 4/7] arm64: dts: renesas: add support for solidrun rzg2l som and hb-iiot evb Josua Mayer
@ 2026-09-02 11:50 ` Josua Mayer
2026-09-02 11:50 ` [PATCH v4 6/7] arm64: dts: renesas: add support for solidrun rzg2lc " Josua Mayer
` (2 subsequent siblings)
7 siblings, 0 replies; 18+ messages in thread
From: Josua Mayer @ 2026-09-02 11:50 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Benjamin Bara, Linus Walleij,
Lad Prabhakar
Cc: Jon Nettleton, Mikhail Anikin, Yazan Shhady, linux-renesas-soc,
devicetree, linux-kernel, linux-usb, linux-gpio, Josua Mayer
Add support for the SolidRun RZ/V2L [1] SoM on Hummingboard IIoT [2].
The SoM features:
- 2x 1Gbps Ethernet with PHY
- eMMC
- 1/2GB DDR
- WiFi + Bluetooth
- SDHI Mux switching between eMMC and Carrier Board
The HummingBoard IIoT features:
- 3x USB-2.0 Type A connector
- 2x 1Gbps RJ45 Ethernet
- USB Type-C Console Port
- microSD connector
- RTC with backup battery
- RGB Status LED
- 1x M.2 B-Key connector with USB-2.0 + SIM card holder
- 1x DSI Display Connector
- GPIO header
- 2x RS232/RS485 ports (configurable)
- 2x CAN
The RZ-V2L SoM shares PCB with RZ/G2L, differing only in the SoC itself.
V2L is adding a powerful DRP-AI NPU which G2L lacks.
Due to the similarities most code is shared, including DT overlays for
eMMC, microSD, and RS485.
[1] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-v2l-som/
[2] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2l-iot-sbc/
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/renesas/Makefile | 13 +++++++++++++
.../boot/dts/renesas/r9a07g054l2-hummingboard-iiot.dts | 16 ++++++++++++++++
2 files changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index e2af196e18bf6..4a0cde8cc3b7d 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -189,6 +189,19 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtbo
r9a07g044l2-smarc-cru-csi-ov5645-dtbs := r9a07g044l2-smarc.dtb r9a07g044l2-smarc-cru-csi-ov5645.dtbo
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtb
+dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-iiot.dtb
+dtb-$(CONFIG_ARCH_R9A07G054) += rzg2l-sr-som-emmc.dtbo
+r9a07g054l2-hummingboard-iiot-emmc-dtbs := r9a07g054l2-hummingboard-iiot.dtb rzg2l-sr-som-emmc.dtbo
+dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-iiot-emmc.dtb
+dtb-$(CONFIG_ARCH_R9A07G054) += rzg2l-hummingboard-iiot-microsd.dtbo
+r9a07g054l2-hummingboard-iiot-microsd-dtbs := r9a07g054l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-microsd.dtbo
+dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-iiot-microsd.dtb
+dtb-$(CONFIG_ARCH_R9A07G054) += rzg2l-hummingboard-iiot-rs485-a.dtbo
+r9a07g054l2-hummingboard-iiot-rs485-a-dtbs := r9a07g054l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo
+dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-iiot-rs485-a.dtb
+dtb-$(CONFIG_ARCH_R9A07G054) += rzg2l-hummingboard-iiot-rs485-b.dtbo
+r9a07g054l2-hummingboard-iiot-rs485-b-dtbs := r9a07g054l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-b.dtbo
+dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-iiot-rs485-b.dtb
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc-cru-csi-ov5645.dtbo
r9a07g054l2-smarc-cru-csi-ov5645-dtbs := r9a07g054l2-smarc.dtb r9a07g054l2-smarc-cru-csi-ov5645.dtbo
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-hummingboard-iiot.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-hummingboard-iiot.dts
new file mode 100644
index 0000000000000..d77a6ff163bea
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-hummingboard-iiot.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+/dts-v1/;
+
+#include "r9a07g054l2.dtsi"
+#include "rzg2l-sr-som.dtsi"
+#include "rzg2l-hummingboard-iiot.dtsi"
+
+/ {
+ compatible = "solidrun,rzv2l-hummingboard-iiot", "solidrun,rzv2l-sr-som",
+ "renesas,r9a07g054l2", "renesas,r9a07g054";
+ model = "SolidRun RZ/V2L HummingBoard IIoT";
+};
--
2.51.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v4 6/7] arm64: dts: renesas: add support for solidrun rzg2lc som and hb-iiot evb
2026-09-02 11:50 [PATCH v4 0/7] arm64: dts: renesas: Add various SolidRun RZ/G2 based boards Josua Mayer
` (4 preceding siblings ...)
2026-09-02 11:50 ` [PATCH v4 5/7] arm64: dts: renesas: add support for solidrun rzv2l " Josua Mayer
@ 2026-09-02 11:50 ` Josua Mayer
2026-09-02 12:03 ` sashiko-bot
2026-09-02 11:50 ` [PATCH v4 7/7] arm64: dts: renesas: rzg2l(c)/rzv2l hb-iiot: add dsi panel dt overlay Josua Mayer
2026-09-02 12:03 ` [PATCH v4 0/7] arm64: dts: renesas: Add various SolidRun RZ/G2 based boards Geert Uytterhoeven
7 siblings, 1 reply; 18+ messages in thread
From: Josua Mayer @ 2026-09-02 11:50 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Benjamin Bara, Linus Walleij,
Lad Prabhakar
Cc: Jon Nettleton, Mikhail Anikin, Yazan Shhady, linux-renesas-soc,
devicetree, linux-kernel, linux-usb, linux-gpio, Josua Mayer
Add support for the SolidRun RZ/G2LC SoM [1] on Hummingboard IIoT [2].
The SoM features:
- 1Gbps Ethernet with PHY
- eMMC
- 1/2GB DDR
- WiFi + Bluetooth
- SDHI Mux switching between eMMC and Carrier Board
The HummingBoard IIoT features:
- 3x USB-2.0 Type A connector
- 1x 1Gbps RJ45 Ethernet
- USB Type-C Console Port
- microSD connector
- RTC with backup battery
- RGB Status LED
- 1x M.2 B-Key connector with USB-2.0 + SIM card holder
- 1x DSI Display Connector
- GPIO header
- 2x RS232/RS485 ports (configurable)
The RZ/G2LC SoM was designed to be pin compatible to G2L SoM, with
slightly reduced feature set.
Descriptions for eMMC, microSD, and RS485 are shared with G2L.
[1] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2lc-som/
[2] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2l-iot-sbc/
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/renesas/Makefile | 9 +
.../dts/renesas/r9a07g044c2-hummingboard-iiot.dts | 20 +
arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi | 416 +++++++++++++++++++++
3 files changed, 445 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 4a0cde8cc3b7d..69b1f75156016 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -165,6 +165,15 @@ dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-du-adv7513.dtb
r9a07g043u11-smarc-pmod-dtbs := r9a07g043u11-smarc.dtb r9a07g043-smarc-pmod.dtbo
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-pmod.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot.dtb
+r9a07g044c2-hummingboard-iiot-emmc-dtbs := r9a07g044c2-hummingboard-iiot.dtb rzg2l-sr-som-emmc.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-emmc.dtb
+r9a07g044c2-hummingboard-iiot-microsd-dtbs := r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-microsd.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-microsd.dtb
+r9a07g044c2-hummingboard-iiot-rs485-a-dtbs := r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-rs485-a.dtb
+r9a07g044c2-hummingboard-iiot-rs485-b-dtbs := r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-b.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-rs485-b.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtbo
r9a07g044c2-smarc-cru-csi-ov5645-dtbs := r9a07g044c2-smarc.dtb r9a07g044c2-smarc-cru-csi-ov5645.dtbo
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-hummingboard-iiot.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-hummingboard-iiot.dts
new file mode 100644
index 0000000000000..9cc21ae32ed4d
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-hummingboard-iiot.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+/dts-v1/;
+
+#include "r9a07g044c2.dtsi"
+#include "rzg2lc-sr-som.dtsi"
+#include "rzg2l-hummingboard-iiot-common.dtsi"
+
+/ {
+ compatible = "solidrun,rzg2lc-hummingboard-iiot", "solidrun,rzg2lc-sr-som",
+ "renesas,r9a07g044c2", "renesas,r9a07g044";
+ model = "SolidRun RZ/G2LC HummingBoard IIoT";
+};
+
+&vmmc {
+ gpios = <&pinctrl RZG2L_GPIO(18, 1) GPIO_ACTIVE_HIGH>;
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi
new file mode 100644
index 0000000000000..468304bdd47b4
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi
@@ -0,0 +1,416 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2LC Solidrun SOM
+ *
+ * Copyright 2023 SolidRun Ltd.
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+/ {
+ aliases {
+ ethernet0 = ð0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ mmc0 = &sdhi0;
+ mmc1 = &sdhi1;
+ rtc0 = &pmic;
+ serial0 = &scif0;
+ serial1 = &scif1;
+ serial2 = &scif2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ sdhi0_mux: mux-controller-0 {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+ #mux-state-cells = <1>;
+ /*
+ * Mux switches SD0_DATA[0-3], SD0_CMD & SD0_CLK between
+ * on-SoM eMMC and board-to-board connector using one gpio:
+ * High = connector, Low = eMMC.
+ * Define active-high for logical mux state 0 = eMMC, 1 = connector.
+ */
+ mux-gpios = <&pinctrl RZG2L_GPIO(22, 1) GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_pmic_buck1: regulator-pmic-buck1 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-buck1";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1100000>;
+ regulator-min-microvolt = <1100000>;
+ };
+
+ reg_pmic_buck3: regulator-pmic-buck3 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-buck3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ };
+
+ reg_pmic_buck4: regulator-pmic-buck4 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-buck4";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ };
+
+ reg_pmic_ldo1: regulator-pmic-ldo1 {
+ compatible = "regulator-gpio";
+ regulator-name = "pmic-ldo1";
+ gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ states = <3300000 1>, <1800000 0>;
+ };
+
+ reg_pmic_ldo2: regulator-pmic-ldo2 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-ldo2";
+ /*
+ * This ldo can switch mmc host controller io voltage between
+ * 1.8V and 3.3V by assembly option of pull-up / pull-dow.
+ * Default assembly is 3.3V.
+ */
+ regulator-min-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ mmp_reserved: linux,multimedia@68000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x68000000 0x0 0x8000000>;
+ reusable;
+ };
+
+ global_cma: linux,cma@58000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x58000000 0x0 0x10000000>;
+ reusable;
+ linux,cma-default;
+ };
+ };
+
+ sdhi1_pwrseq: sdhi1-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pinctrl RZG2L_GPIO(23, 0) GPIO_ACTIVE_LOW>;
+ };
+
+ /* 32.768kHz crystal */
+ x2: x2-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ memory@40000000 {
+ reg = <0x0 0x40000000 0x0 0x40000000>;
+ device_type = "memory";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+ð0 {
+ phy-handle = <&phy0>;
+ pinctrl-0 = <ð0_pins>;
+ pinctrl-names = "default";
+ /*
+ * ravb driver does not configure mac internal delays for RZ/G2L(C),
+ * instead delays are added by the ADIN1200 phy driver.
+ */
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ /* Level interrupts are typical for phy but not supported on rz/g2l gpios. */
+ interrupts-extended = <&pinctrl RZG2L_GPIO(27, 0) IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <24000000>;
+};
+
+&gpu {
+ mali-supply = <®_pmic_buck1>;
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c01";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ pmic: pmic@12 {
+ compatible = "renesas,raa215300";
+ reg = <0x12>, <0x6f>;
+ reg-names = "main", "rtc";
+ clocks = <&x2>;
+ clock-names = "xin";
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ostm1 {
+ status = "okay";
+};
+
+&ostm2 {
+ status = "okay";
+};
+
+&phyrst {
+ status = "okay";
+};
+
+&pinctrl {
+ eth0_pins: eth0 {
+ pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
+ <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
+ <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
+ <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
+ <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
+ <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
+ <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
+ <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
+ <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
+ <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
+ <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
+ <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
+ <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
+ <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
+ <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
+ };
+
+ i2c0_pins: i2c0 {
+ input-enable;
+ pins = "RIIC0_SDA", "RIIC0_SCL";
+ };
+
+ i2c1_pins: i2c1 {
+ input-enable;
+ pins = "RIIC1_SDA", "RIIC1_SCL";
+ };
+
+ i2c2_pins: i2c2 {
+ pinmux = <RZG2L_PORT_PINMUX(42, 3, 1)>, /* RIIC2_SDA */
+ <RZG2L_PORT_PINMUX(42, 4, 1)>; /* RIIC2_SCL */
+ };
+
+ qspi0_pins: qspi0 {
+ pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3",
+ "QSPI0_SPCLK", "QSPI0_SSL";
+ power-source = <1800>;
+ };
+
+ scif0_pins: scif0 {
+ pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* SCIF0_TXD */
+ <RZG2L_PORT_PINMUX(38, 1, 1)>; /* SCIF0_RXD */
+ };
+
+ scif2_pins: scif2 {
+ pinmux = <RZG2L_PORT_PINMUX(42, 0, 4)>, /* SCIF2_TXD */
+ <RZG2L_PORT_PINMUX(42, 1, 4)>, /* SCIF2_RXD */
+ <RZG2L_PORT_PINMUX(5, 1, 2)>, /* SCIF2_CTS# */
+ <RZG2L_PORT_PINMUX(5, 2, 2)>; /* SCIF2_RTS# */
+ };
+
+ sdhi0_4bit_pins: sdhi0-4bit {
+ sd0_ctrl_dat03 {
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
+ "SD0_CLK", "SD0_CMD";
+ power-source = <3300>;
+ };
+
+ /*
+ * Pins 4-7 are hard-wired to eMMC with 1.8V IO voltage,
+ * with all pins sharing a single voltage domain.
+ *
+ * These pins are fixed-function lacking independently configurable
+ * pull-up, pull-down or output-disable.
+ *
+ * While unused, disable the input buffers to avoid sampling the still
+ * physically connected but unused eMMC lines.
+ * For output direction rely on correct controller bus-width configuration
+ * to avoid over-voltage to eMMC e.g. when operating at 3.3V for a 4-bit microSD.
+ */
+ sd0_dat47 {
+ input-disable;
+ pins = "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
+ };
+ };
+
+ sdhi0_4bit_uhs_pins: sdhi0-4bit-uhs {
+ sd0_ctrl_dat03 {
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
+ "SD0_CLK", "SD0_CMD";
+ power-source = <1800>;
+ };
+
+ /*
+ * Pins 4-7 are hard-wired to eMMC with 1.8V IO voltage,
+ * with all pins sharing a single voltage domain.
+ *
+ * These pins are fixed-function lacking independently configurable
+ * pull-up, pull-down or output-disable.
+ *
+ * While unused, disable the input buffers to avoid sampling the still
+ * physically connected but unused eMMC lines.
+ * For output direction rely on correct controller bus-width configuration
+ * to avoid over-voltage to eMMC e.g. when operating at 3.3V for a 4-bit microSD.
+ */
+ sd0_dat47 {
+ input-disable;
+ pins = "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
+ };
+ };
+
+ sdhi0_8bit_uhs_pins: sdhi0-8bit-uhs {
+ input-enable;
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
+ "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7",
+ "SD0_CLK", "SD0_CMD";
+ power-source = <1800>;
+ };
+
+ sdhi0_cd_pins: sdhi0-cd {
+ pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */
+ };
+
+ /* SD0_RST is only routed to eMMC which uses fixed 1.8V IO voltage */
+ sdhi0_rst_pins: sdhi0-rst {
+ pins = "SD0_RST#";
+ power-source = <1800>;
+ };
+
+ sdhi1_pins: sdhi1 {
+ pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3",
+ "SD1_CLK", "SD1_CMD";
+ power-source = <3300>;
+ };
+
+ spi1_pins: spi1 {
+ pinmux = <RZG2L_PORT_PINMUX(44, 2, 1)>, /* RSPI1_MISO */
+ <RZG2L_PORT_PINMUX(44, 1, 1)>, /* RSPI1_MOSI# */
+ <RZG2L_PORT_PINMUX(44, 0, 1)>; /* RSPI1_CK# */
+ };
+
+ spi1_cs_pins: spi1-cs {
+ pinmux = <RZG2L_PORT_PINMUX(44, 3, 1)>; /* RSPI1_SSL */
+ };
+};
+
+&sbc {
+ pinctrl-0 = <&qspi0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ flash@0 {
+ compatible = "winbond,w25q80bl", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ };
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+ status = "okay";
+};
+
+/* WiFi */
+&sdhi1 {
+ /* Murata 1YN max rate is 50MHz */
+ max-frequency = <50000000>;
+ bus-width = <4>;
+ cap-sdio-irq;
+ mmc-pwrseq = <&sdhi1_pwrseq>;
+ non-removable;
+ no-1-8-v;
+ no-sd;
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-names = "default";
+ vmmc-supply = <®_pmic_buck4>;
+ /*
+ * Host controller IO voltage is provided from reg_pmic_ldo2,
+ * WiFi module IO voltage from reg_pmic_buck4.
+ * Neither is configurable at run-time so either can be set here.
+ */
+ vqmmc-supply = <®_pmic_ldo2>;
+ status = "okay";
+};
+
+&usb2_phy0 {
+ vbus-supply = <&usb0_vbus_otg>;
+ status = "okay";
+};
+
+&usb2_phy1 {
+ status = "okay";
+};
+
+&wdt0 {
+ status = "okay";
+};
--
2.51.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v4 6/7] arm64: dts: renesas: add support for solidrun rzg2lc som and hb-iiot evb
2026-09-02 11:50 ` [PATCH v4 6/7] arm64: dts: renesas: add support for solidrun rzg2lc " Josua Mayer
@ 2026-09-02 12:03 ` sashiko-bot
0 siblings, 0 replies; 18+ messages in thread
From: sashiko-bot @ 2026-09-02 12:03 UTC (permalink / raw)
To: Josua Mayer; +Cc: wsa+renesas, conor+dt, robh, devicetree
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Incorrect memory base address in device tree: `0x40000000` instead of `0x48000000`.
--
commit f502b3c798473b8b3737ee55d511455f5f7f315c
Author: Josua Mayer <josua@solid-run.com>
arm64: dts: renesas: add support for solidrun rzg2lc som and hb-iiot evb
This commit adds support for the SolidRun RZ/G2LC SoM and Hummingboard IIoT
evaluation board. It includes the device tree source for the board
components, such as memory mappings, regulators, and interfaces.
> diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi
> new file mode 100644
> index 0000000000000..468304bdd47b4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi
[ ... ]
> + reserved-memory {
> + ranges;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + mmp_reserved: linux,multimedia@68000000 {
> + compatible = "shared-dma-pool";
> + reg = <0x0 0x68000000 0x0 0x8000000>;
> + reusable;
> + };
> +
> + global_cma: linux,cma@58000000 {
> + compatible = "shared-dma-pool";
> + reg = <0x0 0x58000000 0x0 0x10000000>;
> + reusable;
> + linux,cma-default;
> + };
> + };
> +
> + sdhi1_pwrseq: sdhi1-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + reset-gpios = <&pinctrl RZG2L_GPIO(23, 0) GPIO_ACTIVE_LOW>;
> + };
> +
> + /* 32.768kHz crystal */
> + x2: x2-clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + };
> +
> + memory@40000000 {
> + reg = <0x0 0x40000000 0x0 0x40000000>;
[Severity: Medium]
Is this memory base address correct? The RZ/G2L architecture typically
reserves the first 128MB of DDR (0x40000000 - 0x47FFFFFF) for the secure
area (TF-A / TrustZone enclave). If the bootloader doesn't rewrite this,
won't the kernel accessing this range trigger an SError?
Given the reserved-memory nodes at 0x58000000 and 0x68000000, should the
intended base address actually be 0x48000000?
> + device_type = "memory";
> + };
> +};
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260902-rzg2-sr-boards-v4-0-4a456a422fee@solid-run.com?part=6
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v4 7/7] arm64: dts: renesas: rzg2l(c)/rzv2l hb-iiot: add dsi panel dt overlay
2026-09-02 11:50 [PATCH v4 0/7] arm64: dts: renesas: Add various SolidRun RZ/G2 based boards Josua Mayer
` (5 preceding siblings ...)
2026-09-02 11:50 ` [PATCH v4 6/7] arm64: dts: renesas: add support for solidrun rzg2lc " Josua Mayer
@ 2026-09-02 11:50 ` Josua Mayer
2026-09-02 11:59 ` sashiko-bot
2026-09-03 10:06 ` Josua Mayer
2026-09-02 12:03 ` [PATCH v4 0/7] arm64: dts: renesas: Add various SolidRun RZ/G2 based boards Geert Uytterhoeven
7 siblings, 2 replies; 18+ messages in thread
From: Josua Mayer @ 2026-09-02 11:50 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Benjamin Bara, Linus Walleij,
Lad Prabhakar
Cc: Jon Nettleton, Mikhail Anikin, Yazan Shhady, linux-renesas-soc,
devicetree, linux-kernel, linux-usb, linux-gpio, Josua Mayer
The SolidRun Hummingboard IIoT features a DSI connector supporting
touch-screen displays and is usable with RZ/G2L, RZ/G2LC and RZ/V2L
SoMs.
Provide addon for the Winstar WJ70N3TYJHMNG0 1024x600 dsi panel.
Add the addon in Makefile for all supported SoMs SoC targets.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/renesas/Makefile | 8 +++
...hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso | 74 ++++++++++++++++++++++
2 files changed, 82 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 69b1f75156016..0bc2bbff9370f 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -170,6 +170,8 @@ r9a07g044c2-hummingboard-iiot-emmc-dtbs := r9a07g044c2-hummingboard-iiot.dtb rzg
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-emmc.dtb
r9a07g044c2-hummingboard-iiot-microsd-dtbs := r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-microsd.dtbo
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-microsd.dtb
+r9a07g044c2-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0-dtbs := r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtb
r9a07g044c2-hummingboard-iiot-rs485-a-dtbs := r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-rs485-a.dtb
r9a07g044c2-hummingboard-iiot-rs485-b-dtbs := r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-b.dtbo
@@ -186,6 +188,9 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-emmc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-microsd.dtbo
r9a07g044l2-hummingboard-iiot-microsd-dtbs := r9a07g044l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-microsd.dtbo
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-microsd.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtbo
+r9a07g044l2-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0-dtbs := r9a07g044l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-rs485-a.dtbo
r9a07g044l2-hummingboard-iiot-rs485-a-dtbs := r9a07g044l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-rs485-a.dtb
@@ -205,6 +210,9 @@ dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-iiot-emmc.dtb
dtb-$(CONFIG_ARCH_R9A07G054) += rzg2l-hummingboard-iiot-microsd.dtbo
r9a07g054l2-hummingboard-iiot-microsd-dtbs := r9a07g054l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-microsd.dtbo
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-iiot-microsd.dtb
+dtb-$(CONFIG_ARCH_R9A07G054) += rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtbo
+r9a07g054l2-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0-dtbs := r9a07g054l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtbo
+dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtb
dtb-$(CONFIG_ARCH_R9A07G054) += rzg2l-hummingboard-iiot-rs485-a.dtbo
r9a07g054l2-hummingboard-iiot-rs485-a-dtbs := r9a07g054l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-iiot-rs485-a.dtb
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso
new file mode 100644
index 0000000000000..e43a38d5330e6
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ *
+ * Overlay for enabling HummingBoard IIoT MIPI-DSI connector
+ * with Winstar WJ70N3TYJHMNG0 panel.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+&{/} {
+ dsi_backlight: dsi-backlight {
+ compatible = "gpio-backlight";
+ gpios = <&tca6408_u48 3 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&i2c_dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen@41 {
+ compatible = "ilitek,ili2130";
+ reg = <0x41>;
+ /*
+ * Touchscreen fires short active-low pulses which level trigger
+ * on i2c gpio expander can miss. Trigger on falling edge instead.
+ */
+ interrupts-extended = <&tca6416_u21 13 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&tca6408_u48 6 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ panel@0 {
+ /* This is a Winstar panel, but the ronbo panel uses same controls. */
+ compatible = "ronbo,rb070d30";
+ reg = <0>;
+ /* reset is active-low but driver inverts it internally */
+ reset-gpios = <&tca6408_u48 1 GPIO_ACTIVE_HIGH>;
+ backlight = <&dsi_backlight>;
+ power-gpios = <&tca6408_u48 2 GPIO_ACTIVE_HIGH>;
+ shlr-gpios = <&tca6408_u48 4 GPIO_ACTIVE_LOW>;
+ updn-gpios = <&tca6408_u48 5 GPIO_ACTIVE_HIGH>;
+ vcc-lcd-supply = <®_dsi_panel>;
+
+ port {
+ dsi_in_panel: endpoint {
+ remote-endpoint = <&mipi_dsi_out>;
+ };
+ };
+ };
+
+ ports {
+ port@1 {
+ mipi_dsi_out: endpoint {
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&dsi_in_panel>;
+ };
+ };
+ };
+};
+
+&du {
+ status = "okay";
+};
--
2.51.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v4 7/7] arm64: dts: renesas: rzg2l(c)/rzv2l hb-iiot: add dsi panel dt overlay
2026-09-02 11:50 ` [PATCH v4 7/7] arm64: dts: renesas: rzg2l(c)/rzv2l hb-iiot: add dsi panel dt overlay Josua Mayer
@ 2026-09-02 11:59 ` sashiko-bot
2026-09-03 10:06 ` Josua Mayer
1 sibling, 0 replies; 18+ messages in thread
From: sashiko-bot @ 2026-09-02 11:59 UTC (permalink / raw)
To: Josua Mayer; +Cc: conor+dt, wsa+renesas, robh, devicetree
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Medium] The device tree overlay intentionally misrepresents the reset GPIO polarity to work around a Linux driver bug.
- [Medium] The panel node omits the exact hardware compatible string, using only a fallback compatible string from a different vendor's panel.
- [Low] Missing 'reg' property in node 'port@1'.
--
commit 8ad6ab9479d146e186e59ea48122ed17c1b07e32
Author: Josua Mayer <josua@solid-run.com>
arm64: dts: renesas: rzg2l(c)/rzv2l hb-iiot: add dsi panel dt overlay
This commit adds a device tree overlay for the Winstar WJ70N3TYJHMNG0
1024x600 DSI panel used on the SolidRun Hummingboard IIoT. The overlay
enables the MIPI-DSI connector and configures the panel, touchscreen,
and backlight for supported RZ/G2L, RZ/G2LC, and RZ/V2L targets.
[ ... ]
> diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso
> new file mode 100644
> index 0000000000000..e43a38d5330e6
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso
> @@ -0,0 +1,74 @@
[ ... ]
> +&dsi {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + panel@0 {
> + /* This is a Winstar panel, but the ronbo panel uses same controls. */
> + compatible = "ronbo,rb070d30";
[Severity: Medium]
Is it possible to include the exact hardware compatible string for the Winstar
WJ70N3TYJHMNG0 panel before the fallback?
Core Devicetree principles require the compatible property to identify the
specific hardware part first, followed by any fallback identifiers. Providing
only the fallback string masks the true hardware identity. This might make it
difficult for the OS to apply future device-specific quirks or optimizations
without modifying the DT.
> + reg = <0>;
> + /* reset is active-low but driver inverts it internally */
> + reset-gpios = <&tca6408_u48 1 GPIO_ACTIVE_HIGH>;
[Severity: Medium]
Does this property intentionally misrepresent the physical hardware state
(active-low reset) as active-high to accommodate a defect in the driver logic?
The device tree is intended to describe hardware accurately and
OS-independently. Encoding a software workaround into the hardware description
couples the DT to a specific buggy version of the Linux panel driver. This
breaks compatibility with other operating systems and will cause the panel to
break in Linux if the driver is ever fixed to properly handle standard reset
semantics.
> + backlight = <&dsi_backlight>;
> + power-gpios = <&tca6408_u48 2 GPIO_ACTIVE_HIGH>;
> + shlr-gpios = <&tca6408_u48 4 GPIO_ACTIVE_LOW>;
> + updn-gpios = <&tca6408_u48 5 GPIO_ACTIVE_HIGH>;
> + vcc-lcd-supply = <®_dsi_panel>;
> +
> + port {
> + dsi_in_panel: endpoint {
> + remote-endpoint = <&mipi_dsi_out>;
> + };
> + };
> + };
> +
> + ports {
> + port@1 {
[Severity: Low]
Is this node missing a 'reg = <1>;' property?
The Device Tree specification requires that any node with a unit address (e.g.,
@1) must have a matching reg property. Missing this property causes the Device
Tree Compiler (dtc) to emit a unit_address_vs_reg warning during the build.
> + mipi_dsi_out: endpoint {
> + data-lanes = <1 2 3 4>;
> + remote-endpoint = <&dsi_in_panel>;
> + };
> + };
> + };
> +};
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260902-rzg2-sr-boards-v4-0-4a456a422fee@solid-run.com?part=7
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v4 7/7] arm64: dts: renesas: rzg2l(c)/rzv2l hb-iiot: add dsi panel dt overlay
2026-09-02 11:50 ` [PATCH v4 7/7] arm64: dts: renesas: rzg2l(c)/rzv2l hb-iiot: add dsi panel dt overlay Josua Mayer
2026-09-02 11:59 ` sashiko-bot
@ 2026-09-03 10:06 ` Josua Mayer
1 sibling, 0 replies; 18+ messages in thread
From: Josua Mayer @ 2026-09-03 10:06 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Benjamin Bara, Linus Walleij,
Lad Prabhakar
Cc: Jon Nettleton, Mikhail Anikin, Yazan Shhady,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org,
linux-gpio@vger.kernel.org
Am 02.09.26 um 13:50 schrieb Josua Mayer:
> The SolidRun Hummingboard IIoT features a DSI connector supporting
> touch-screen displays and is usable with RZ/G2L, RZ/G2LC and RZ/V2L
> SoMs.
>
> Provide addon for the Winstar WJ70N3TYJHMNG0 1024x600 dsi panel.
>
> Add the addon in Makefile for all supported SoMs SoC targets.
>
> Signed-off-by: Josua Mayer <josua@solid-run.com>
> ---
> arch/arm64/boot/dts/renesas/Makefile | 8 +++
> ...hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso | 74 ++++++++++++++++++++++
> 2 files changed, 82 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
> index 69b1f75156016..0bc2bbff9370f 100644
> --- a/arch/arm64/boot/dts/renesas/Makefile
> +++ b/arch/arm64/boot/dts/renesas/Makefile
> @@ -170,6 +170,8 @@ r9a07g044c2-hummingboard-iiot-emmc-dtbs := r9a07g044c2-hummingboard-iiot.dtb rzg
> dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-emmc.dtb
> r9a07g044c2-hummingboard-iiot-microsd-dtbs := r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-microsd.dtbo
> dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-microsd.dtb
> +r9a07g044c2-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0-dtbs := r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtbo
> +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtb
> r9a07g044c2-hummingboard-iiot-rs485-a-dtbs := r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo
> dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-rs485-a.dtb
> r9a07g044c2-hummingboard-iiot-rs485-b-dtbs := r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-b.dtbo
> @@ -186,6 +188,9 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-emmc.dtb
> dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-microsd.dtbo
> r9a07g044l2-hummingboard-iiot-microsd-dtbs := r9a07g044l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-microsd.dtbo
> dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-microsd.dtb
> +dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtbo
> +r9a07g044l2-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0-dtbs := r9a07g044l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtbo
> +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtb
> dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-rs485-a.dtbo
> r9a07g044l2-hummingboard-iiot-rs485-a-dtbs := r9a07g044l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo
> dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-rs485-a.dtb
> @@ -205,6 +210,9 @@ dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-iiot-emmc.dtb
> dtb-$(CONFIG_ARCH_R9A07G054) += rzg2l-hummingboard-iiot-microsd.dtbo
> r9a07g054l2-hummingboard-iiot-microsd-dtbs := r9a07g054l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-microsd.dtbo
> dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-iiot-microsd.dtb
> +dtb-$(CONFIG_ARCH_R9A07G054) += rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtbo
> +r9a07g054l2-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0-dtbs := r9a07g054l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtbo
> +dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtb
> dtb-$(CONFIG_ARCH_R9A07G054) += rzg2l-hummingboard-iiot-rs485-a.dtbo
> r9a07g054l2-hummingboard-iiot-rs485-a-dtbs := r9a07g054l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo
> dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-iiot-rs485-a.dtb
> diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso
> new file mode 100644
> index 0000000000000..e43a38d5330e6
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso
> @@ -0,0 +1,74 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Copyright 2025 Josua Mayer <josua@solid-run.com>
> + *
> + * Overlay for enabling HummingBoard IIoT MIPI-DSI connector
> + * with Winstar WJ70N3TYJHMNG0 panel.
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +&{/} {
> + dsi_backlight: dsi-backlight {
> + compatible = "gpio-backlight";
> + gpios = <&tca6408_u48 3 GPIO_ACTIVE_LOW>;
> + };
> +};
> +
> +&i2c_dsi {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + touchscreen@41 {
> + compatible = "ilitek,ili2130";
> + reg = <0x41>;
> + /*
> + * Touchscreen fires short active-low pulses which level trigger
> + * on i2c gpio expander can miss. Trigger on falling edge instead.
> + */
> + interrupts-extended = <&tca6416_u21 13 IRQ_TYPE_EDGE_FALLING>;
> + reset-gpios = <&tca6408_u48 6 GPIO_ACTIVE_LOW>;
> + };
> +};
> +
> +&dsi {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + panel@0 {
> + /* This is a Winstar panel, but the ronbo panel uses same controls. */
> + compatible = "ronbo,rb070d30";
Sashiko flagged the compatible string, suggesting a winstar-specific one.
I disagree it does not seem worth it, as the panels are very similar in
specs and behaviour.
Further ronbo panel currently has a single in-tree user, and now gets
one more:
arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso: compatible = "ronbo,rb070d30";
arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso: compatible = "ronbo,rb070d30";
Any opinions on adding winstar compatible string to bindings?
> + reg = <0>;
> + /* reset is active-low but driver inverts it internally */
> + reset-gpios = <&tca6408_u48 1 GPIO_ACTIVE_HIGH>;
> + backlight = <&dsi_backlight>;
> + power-gpios = <&tca6408_u48 2 GPIO_ACTIVE_HIGH>;
> + shlr-gpios = <&tca6408_u48 4 GPIO_ACTIVE_LOW>;
> + updn-gpios = <&tca6408_u48 5 GPIO_ACTIVE_HIGH>;
> + vcc-lcd-supply = <®_dsi_panel>;
> +
> + port {
> + dsi_in_panel: endpoint {
> + remote-endpoint = <&mipi_dsi_out>;
> + };
> + };
> + };
> +
> + ports {
> + port@1 {
> + mipi_dsi_out: endpoint {
> + data-lanes = <1 2 3 4>;
> + remote-endpoint = <&dsi_in_panel>;
> + };
Sashiko flagged that port@1 is missing a reg property.
Since this is a dt addon and the base already sets reg I omitted it.
However other properties e.g. #address-cells are added even when the base
already has them.
Any opinions on duplicating reg too?
> + };
> + };
> +};
> +
> +&du {
> + status = "okay";
> +};
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v4 0/7] arm64: dts: renesas: Add various SolidRun RZ/G2 based boards
2026-09-02 11:50 [PATCH v4 0/7] arm64: dts: renesas: Add various SolidRun RZ/G2 based boards Josua Mayer
` (6 preceding siblings ...)
2026-09-02 11:50 ` [PATCH v4 7/7] arm64: dts: renesas: rzg2l(c)/rzv2l hb-iiot: add dsi panel dt overlay Josua Mayer
@ 2026-09-02 12:03 ` Geert Uytterhoeven
7 siblings, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2026-09-02 12:03 UTC (permalink / raw)
To: Josua Mayer
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Greg Kroah-Hartman, Benjamin Bara, Linus Walleij, Lad Prabhakar,
Jon Nettleton, Mikhail Anikin, Yazan Shhady, linux-renesas-soc,
devicetree, linux-kernel, linux-usb, linux-gpio, Conor Dooley,
Krzysztof Kozlowski
Hi Joshua,
On Wed, 2 Sept 2026 at 13:50, Josua Mayer <josua@solid-run.com> wrote:
> Add support for a variety of SolidRun RZ/G2 based SoMs and the
> HummingBoard IIoT Evaluation board.
Thanks for your series!
> Changes in v7:
Oops, subject says v4?
Fortunately b4 is not confused, and does The Right Thing(tm)...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread