* [PATCH v5 1/6] dt-bindings: vendor-prefixes: Add AYN Technologies
2026-04-08 19:41 [PATCH v5 0/6] arm64: dts: qcom: Support AYN QCS8550 Devices Aaron Kling via B4 Relay
@ 2026-04-08 19:41 ` Aaron Kling via B4 Relay
2026-04-08 19:41 ` [PATCH v5 2/6] dt-bindings: arm: qcom: Add AYN QCS8550 Devices Aaron Kling via B4 Relay
` (4 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Aaron Kling via B4 Relay @ 2026-04-08 19:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Aaron Kling, Xilin Wu,
Krzysztof Kozlowski
From: Xilin Wu <wuxilin123@gmail.com>
Add an entry for AYN Technologies (https://www.ayntec.com/)
Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 28784d66ae7ba5..b891d6d41f198a 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -225,6 +225,8 @@ patternProperties:
description: Axis Communications AB
"^ayaneo,.*":
description: Anyun Intelligent Technology (Hong Kong) Co., Ltd
+ "^ayntec,.*":
+ description: AYN Technologies Co., Ltd.
"^azoteq,.*":
description: Azoteq (Pty) Ltd
"^azw,.*":
--
2.53.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v5 2/6] dt-bindings: arm: qcom: Add AYN QCS8550 Devices
2026-04-08 19:41 [PATCH v5 0/6] arm64: dts: qcom: Support AYN QCS8550 Devices Aaron Kling via B4 Relay
2026-04-08 19:41 ` [PATCH v5 1/6] dt-bindings: vendor-prefixes: Add AYN Technologies Aaron Kling via B4 Relay
@ 2026-04-08 19:41 ` Aaron Kling via B4 Relay
2026-04-08 19:41 ` [PATCH v5 3/6] arm64: dts: qcom: Add AYN QCS8550 Common Aaron Kling via B4 Relay
` (3 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Aaron Kling via B4 Relay @ 2026-04-08 19:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Aaron Kling,
Krzysztof Kozlowski
From: Aaron Kling <webgeek1234@gmail.com>
Namely:
* Odin 2
* Odin 2 Mini
* Odin 2 Portal
* Thor
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index b4943123d2e425..4a6733eaa8b14d 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -1099,6 +1099,15 @@ properties:
- const: qcom,qcs8550
- const: qcom,sm8550
+ - items:
+ - enum:
+ - ayntec,odin2
+ - ayntec,odin2mini
+ - ayntec,odin2portal
+ - ayntec,thor
+ - const: qcom,qcs8550
+ - const: qcom,sm8550
+
- items:
- enum:
- ayaneo,pocket-s2
--
2.53.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v5 3/6] arm64: dts: qcom: Add AYN QCS8550 Common
2026-04-08 19:41 [PATCH v5 0/6] arm64: dts: qcom: Support AYN QCS8550 Devices Aaron Kling via B4 Relay
2026-04-08 19:41 ` [PATCH v5 1/6] dt-bindings: vendor-prefixes: Add AYN Technologies Aaron Kling via B4 Relay
2026-04-08 19:41 ` [PATCH v5 2/6] dt-bindings: arm: qcom: Add AYN QCS8550 Devices Aaron Kling via B4 Relay
@ 2026-04-08 19:41 ` Aaron Kling via B4 Relay
2026-04-24 12:11 ` Konrad Dybcio
2026-04-08 19:41 ` [PATCH v5 4/6] arm64: dts: qcom: Add AYN Odin 2 Mini Aaron Kling via B4 Relay
` (2 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Aaron Kling via B4 Relay @ 2026-04-08 19:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Aaron Kling,
Teguh Sobirin
From: Teguh Sobirin <teguh@sobir.in>
This contains everything common between the AYN QCS8550 devices. It will
be included by device specific dts'.
Signed-off-by: Teguh Sobirin <teguh@sobir.in>
Co-developed-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
.../arm64/boot/dts/qcom/qcs8550-ayntec-common.dtsi | 1762 ++++++++++++++++++++
1 file changed, 1762 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayntec-common.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-ayntec-common.dtsi
new file mode 100644
index 00000000000000..e0befc8dc6dfdc
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-ayntec-common.dtsi
@@ -0,0 +1,1762 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Teguh Sobirin.
+ */
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "qcs8550.dtsi"
+#include "pm8550.dtsi"
+#include "pm8550b.dtsi"
+#define PMK8550VE_SID 5
+#include "pm8550ve.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmk8550.dtsi"
+
+/delete-node/ &aop_image_mem;
+/delete-node/ &aop_config_mem;
+/delete-node/ &camera_mem;
+/delete-node/ &ipa_fw_mem;
+/delete-node/ &ipa_gsi_mem;
+/delete-node/ &mpss_dsm_mem;
+/delete-node/ &mpss_mem;
+/delete-node/ &q6_mpss_dtb_mem;
+/delete-node/ &remoteproc_mpss;
+
+/ {
+ chassis-type = "handset";
+
+ aliases {
+ serial0 = &uart7;
+ serial1 = &uart14;
+ };
+
+ // The tzlog label is required by ABL to apply a dtbo, but it can be on any node
+ qcom_tzlog: chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_n>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ debounce-interval = <15>;
+ gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ pmic-glink {
+ compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_sbu: endpoint {
+ remote-endpoint = <&usb0_sbu_mux>;
+ };
+ };
+ };
+ };
+ };
+
+ pwm_fan: pwm-fan {
+ compatible = "pwm-fan";
+
+ fan-supply = <&vdd_fan_5v0>;
+ pwms = <&pm8550_pwm 3 50000>;
+
+ pinctrl-0 = <&fan_pwm_active>, <&fan_int>;
+ pinctrl-names = "default";
+
+ pulses-per-revolution = <4>;
+ interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>;
+
+ cooling-levels = <0 40 65 75 90 100 120 150 175>;
+ #cooling-cells = <2>;
+ };
+
+ reserved-memory {
+ hyp_mem: hyp-region@80000000 {
+ reg = <0 0x80000000 0 0xa00000>;
+ no-map;
+ };
+
+ cpusys_vm_mem: cpusys-vm-region@80a00000 {
+ reg = <0 0x80a00000 0 0x400000>;
+ no-map;
+ };
+
+ hyp_tags_mem: hyp-tags-region@80e00000 {
+ reg = <0 0x80e00000 0 0x3d0000>;
+ no-map;
+ };
+
+ xbl_sc_mem: xbl-sc-region@d8100000 {
+ reg = <0 0xd8100000 0 0x40000>;
+ no-map;
+ };
+
+ hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 {
+ reg = <0 0x811d0000 0 0x30000>;
+ no-map;
+ };
+
+ xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 {
+ reg = <0 0x81a00000 0 0x260000>;
+ no-map;
+ };
+
+ aop_config_merged_mem: aop-config-merged-region@81c80000 {
+ reg = <0 0x81c80000 0 0x74000>;
+ no-map;
+ };
+
+ chipinfo_mem: chipinfo-region@81cf4000 {
+ reg = <0 0x81cf4000 0 0x1000>;
+ no-map;
+ };
+
+ global_sync_mem: global-sync-region@82600000 {
+ reg = <0 0x82600000 0 0x100000>;
+ no-map;
+ };
+
+ tz_stat_mem: tz-stat-region@82700000 {
+ reg = <0 0x82700000 0 0x100000>;
+ no-map;
+ };
+
+ cpucp_fw_mem: cpucp-fw-region@d8140000 {
+ reg = <0 0xd8140000 0 0x1c0000>;
+ no-map;
+ };
+
+ qtee_mem: qtee-region@d8300000 {
+ reg = <0 0xd8300000 0 0x500000>;
+ no-map;
+ };
+
+ hwfence_shbuf: hwfence-shbuf-region@e6440000 {
+ reg = <0 0xe6440000 0 0x2dd000>;
+ no-map;
+ };
+
+ hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 {
+ reg = <0 0xff700000 0 0x100000>;
+ no-map;
+ };
+
+ llcc_lpi_mem: llcc_lpi_region@ff800000 {
+ reg = <0 0xff800000 0 0x600000>;
+ no-map;
+ };
+
+ hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 {
+ reg = <0 0xfce00000 0 0x2900000>;
+ no-map;
+ };
+ };
+
+ sound {
+ compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard";
+ pinctrl-0 = <&lpi_i2s3_active>;
+ pinctrl-names = "default";
+
+ model = "AYN-Odin2";
+ audio-routing = "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "AMIC2", "MIC BIAS2",
+ "TX SWR_INPUT1", "ADC2_OUTPUT";
+
+ speaker-i2s-dai-link {
+ link-name = "Primary MI2S Playback";
+
+ codec {
+ sound-dai = <&spk_amp_l>, <&spk_amp_r>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wcd-playback-dai-link {
+ link-name = "WCD Playback";
+
+ codec {
+ sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wcd-capture-dai-link {
+ link-name = "WCD Capture";
+
+ codec {
+ sound-dai = <&wcd938x 1>, <&swr2 0>, <&lpass_txmacro 0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ dp0-dai-link {
+ link-name = "DP0 Playback";
+
+ codec {
+ sound-dai = <&mdss_dp0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+ };
+
+ thermal-zones {
+ cpu0-thermal {
+ polling-delay = <200>;
+
+ trips {
+ cpuss0_active0: cpu-active0 {
+ temperature = <50000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active1: cpu-active1 {
+ temperature = <55000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active2: cpu-active2 {
+ temperature = <60000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active3: cpu-active3 {
+ temperature = <65000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active4: cpu-active4 {
+ temperature = <70000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active5: cpu-active5 {
+ temperature = <75000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active6: cpu-active6 {
+ temperature = <80000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss0_active7: cpu-active7 {
+ temperature = <85000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ cooling-device = <&pwm_fan 0 1>;
+ trip = <&cpuss0_active0>;
+ };
+
+ map1 {
+ cooling-device = <&pwm_fan 1 2>;
+ trip = <&cpuss0_active1>;
+ };
+
+ map2 {
+ cooling-device = <&pwm_fan 2 3>;
+ trip = <&cpuss0_active2>;
+ };
+
+ map3 {
+ cooling-device = <&pwm_fan 3 4>;
+ trip = <&cpuss0_active3>;
+ };
+
+ map4 {
+ cooling-device = <&pwm_fan 4 5>;
+ trip = <&cpuss0_active4>;
+ };
+
+ map5 {
+ cooling-device = <&pwm_fan 5 6>;
+ trip = <&cpuss0_active5>;
+ };
+
+ map6 {
+ cooling-device = <&pwm_fan 6 7>;
+ trip = <&cpuss0_active6>;
+ };
+
+ map7 {
+ cooling-device = <&pwm_fan 7 8>;
+ trip = <&cpuss0_active7>;
+ };
+ };
+ };
+
+ cpu3-bottom-thermal {
+ polling-delay = <200>;
+
+ trips {
+ cpuss3_active0: cpu-active0 {
+ temperature = <50000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss3_active1: cpu-active1 {
+ temperature = <55000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss3_active2: cpu-active2 {
+ temperature = <60000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss3_active3: cpu-active3 {
+ temperature = <65000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss3_active4: cpu-active4 {
+ temperature = <70000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss3_active5: cpu-active5 {
+ temperature = <75000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss3_active6: cpu-active6 {
+ temperature = <80000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss3_active7: cpu-active7 {
+ temperature = <85000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ cooling-device = <&pwm_fan 0 1>;
+ trip = <&cpuss3_active0>;
+ };
+
+ map1 {
+ cooling-device = <&pwm_fan 1 2>;
+ trip = <&cpuss3_active1>;
+ };
+
+ map2 {
+ cooling-device = <&pwm_fan 2 3>;
+ trip = <&cpuss3_active2>;
+ };
+
+ map3 {
+ cooling-device = <&pwm_fan 3 4>;
+ trip = <&cpuss3_active3>;
+ };
+
+ map4 {
+ cooling-device = <&pwm_fan 4 5>;
+ trip = <&cpuss3_active4>;
+ };
+
+ map5 {
+ cooling-device = <&pwm_fan 5 6>;
+ trip = <&cpuss3_active5>;
+ };
+
+ map6 {
+ cooling-device = <&pwm_fan 6 7>;
+ trip = <&cpuss3_active6>;
+ };
+
+ map7 {
+ cooling-device = <&pwm_fan 7 8>;
+ trip = <&cpuss3_active7>;
+ };
+ };
+ };
+
+ cpu7-bottom-thermal {
+ polling-delay = <200>;
+
+ trips {
+ cpuss7_active0: cpu-active0 {
+ temperature = <50000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss7_active1: cpu-active1 {
+ temperature = <55000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss7_active2: cpu-active2 {
+ temperature = <60000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss7_active3: cpu-active3 {
+ temperature = <65000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss7_active4: cpu-active4 {
+ temperature = <70000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss7_active5: cpu-active5 {
+ temperature = <75000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss7_active6: cpu-active6 {
+ temperature = <80000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpuss7_active7: cpu-active7 {
+ temperature = <85000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ cooling-device = <&pwm_fan 0 1>;
+ trip = <&cpuss7_active0>;
+ };
+
+ map1 {
+ cooling-device = <&pwm_fan 1 2>;
+ trip = <&cpuss7_active1>;
+ };
+
+ map2 {
+ cooling-device = <&pwm_fan 2 3>;
+ trip = <&cpuss7_active2>;
+ };
+
+ map3 {
+ cooling-device = <&pwm_fan 3 4>;
+ trip = <&cpuss7_active3>;
+ };
+
+ map4 {
+ cooling-device = <&pwm_fan 4 5>;
+ trip = <&cpuss7_active4>;
+ };
+
+ map5 {
+ cooling-device = <&pwm_fan 5 6>;
+ trip = <&cpuss7_active5>;
+ };
+
+ map6 {
+ cooling-device = <&pwm_fan 6 7>;
+ trip = <&cpuss7_active6>;
+ };
+
+ map7 {
+ cooling-device = <&pwm_fan 7 8>;
+ trip = <&cpuss7_active7>;
+ };
+ };
+ };
+
+ gpuss-0-thermal {
+ polling-delay = <200>;
+
+ trips {
+ gpuss0_active0: gpu-active0 {
+ temperature = <50000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ gpuss0_active1: gpu-active1 {
+ temperature = <55000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ gpuss0_active2: gpu-active2 {
+ temperature = <60000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ gpuss0_active3: gpu-active3 {
+ temperature = <65000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ gpuss0_active4: gpu-active4 {
+ temperature = <70000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ gpuss0_active5: gpu-active5 {
+ temperature = <75000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ gpuss0_active6: gpu-active6 {
+ temperature = <80000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ gpuss0_active7: gpu-active7 {
+ temperature = <85000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ cooling-device = <&pwm_fan 0 1>;
+ trip = <&gpuss0_active0>;
+ };
+
+ map1 {
+ cooling-device = <&pwm_fan 1 2>;
+ trip = <&gpuss0_active1>;
+ };
+
+ map2 {
+ cooling-device = <&pwm_fan 2 3>;
+ trip = <&gpuss0_active2>;
+ };
+
+ map3 {
+ cooling-device = <&pwm_fan 3 4>;
+ trip = <&gpuss0_active3>;
+ };
+
+ map4 {
+ cooling-device = <&pwm_fan 4 5>;
+ trip = <&gpuss0_active4>;
+ };
+
+ map5 {
+ cooling-device = <&pwm_fan 5 6>;
+ trip = <&gpuss0_active5>;
+ };
+
+ map6 {
+ cooling-device = <&pwm_fan 6 7>;
+ trip = <&gpuss0_active6>;
+ };
+
+ map7 {
+ cooling-device = <&pwm_fan 7 8>;
+ trip = <&gpuss0_active7>;
+ };
+ };
+ };
+ };
+
+ usb0-sbu-mux {
+ compatible = "pericom,pi3usb102", "gpio-sbu-mux";
+
+ enable-gpios = <&tlmm 140 GPIO_ACTIVE_LOW>;
+ select-gpios = <&tlmm 141 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&usb0_sbu_default>;
+ pinctrl-names = "default";
+
+ mode-switch;
+ orientation-switch;
+
+ port {
+ usb0_sbu_mux: endpoint {
+ remote-endpoint = <&pmic_glink_sbu>;
+ };
+ };
+ };
+
+ vdd_fan_5v0: vdd-fan-5v0-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_fan_5v0";
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&tlmm 109 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&fan_pwr_active>;
+ pinctrl-names = "default";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_mcu_3v3: vdd-mcu-3v3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mcu_3v3";
+
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ };
+
+ vph_pwr: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ wcd938x: audio-codec {
+ compatible = "qcom,wcd9385-codec";
+
+ pinctrl-0 = <&wcd_default>;
+ pinctrl-names = "default";
+
+ qcom,micbias1-microvolt = <1800000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <1800000>;
+ qcom,micbias4-microvolt = <1800000>;
+ qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000
+ 500000 500000 500000 500000>;
+ qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+ qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+ qcom,rx-device = <&wcd_rx>;
+ qcom,tx-device = <&wcd_tx>;
+
+ reset-gpios = <&tlmm 108 GPIO_ACTIVE_LOW>;
+
+ vdd-buck-supply = <&vreg_l15b_1p8>;
+ vdd-rxtx-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l15b_1p8>;
+ vdd-mic-bias-supply = <&vreg_bob1>;
+
+ #sound-dai-cells = <1>;
+ };
+
+ wcn7850-pmu {
+ compatible = "qcom,wcn7850-pmu";
+
+ pinctrl-0 = <&wlan_en>, <&bt_default>, <&pmk8550_sleep_clk>;
+ pinctrl-names = "default";
+
+ wlan-enable-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>;
+ bt-enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <&vreg_s5g_0p8>;
+ vddio-supply = <&vreg_l15b_1p8>;
+ vddaon-supply = <&vreg_s2g_0p8>;
+ vdddig-supply = <&vreg_s4e_0p95>;
+ vddrfa1p2-supply = <&vreg_s4g_1p3>;
+ vddrfa1p8-supply = <&vreg_s6g_1p8>;
+
+ regulators {
+ vreg_pmu_rfa_cmn: ldo0 {
+ regulator-name = "vreg_pmu_rfa_cmn";
+ };
+
+ vreg_pmu_aon_0p59: ldo1 {
+ regulator-name = "vreg_pmu_aon_0p59";
+ };
+
+ vreg_pmu_wlcx_0p8: ldo2 {
+ regulator-name = "vreg_pmu_wlcx_0p8";
+ };
+
+ vreg_pmu_wlmx_0p85: ldo3 {
+ regulator-name = "vreg_pmu_wlmx_0p85";
+ };
+
+ vreg_pmu_btcmx_0p85: ldo4 {
+ regulator-name = "vreg_pmu_btcmx_0p85";
+ };
+
+ vreg_pmu_rfa_0p8: ldo5 {
+ regulator-name = "vreg_pmu_rfa_0p8";
+ };
+
+ vreg_pmu_rfa_1p2: ldo6 {
+ regulator-name = "vreg_pmu_rfa_1p2";
+ };
+
+ vreg_pmu_rfa_1p8: ldo7 {
+ regulator-name = "vreg_pmu_rfa_1p8";
+ };
+
+ vreg_pmu_pcie_0p9: ldo8 {
+ regulator-name = "vreg_pmu_pcie_0p9";
+ };
+
+ vreg_pmu_pcie_1p8: ldo9 {
+ regulator-name = "vreg_pmu_pcie_1p8";
+ };
+ };
+ };
+
+ // The arch_timer label is unused here, but is required by ABL to apply a dtbo
+ arch_timer: timer { };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l1-l4-l10-supply = <&vreg_s6g_1p8>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l3-supply = <&vreg_s4g_1p3>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob1>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l11-supply = <&vreg_s4g_1p3>;
+ vdd-l12-supply = <&vreg_s6g_1p8>;
+ vdd-l15-supply = <&vreg_s6g_1p8>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2720000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3104000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p2: ldo11 {
+ regulator-name = "vreg_l11b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_2p8: ldo16 {
+ regulator-name = "vreg_l16b_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-l1-supply = <&vreg_s4g_1p3>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+
+ vreg_l3c_0p9: ldo3 {
+ regulator-name = "vreg_l3c_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "d";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+
+ vreg_l1d_0p88: ldo1 {
+ regulator-name = "vreg_l1d_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4g_1p3>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+
+ vreg_s4e_0p95: smps4 {
+ regulator-name = "vreg_s4e_0p95";
+ regulator-min-microvolt = <904000>;
+ regulator-max-microvolt = <984000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5e_1p08: smps5 {
+ regulator-name = "vreg_s5e_1p08";
+ regulator-min-microvolt = <1010000>;
+ regulator-max-microvolt = <1120000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1e_0p88: ldo1 {
+ regulator-name = "vreg_l1e_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2e_0p9: ldo2 {
+ regulator-name = "vreg_l2e_0p9";
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3e_1p2: ldo3 {
+ regulator-name = "vreg_l3e_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+ vdd-s4-supply = <&vph_pwr>;
+
+ vreg_s4f_0p5: smps4 {
+ regulator-name = "vreg_s4f_0p5";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <700000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1f_0p9: ldo1 {
+ regulator-name = "vreg_l1f_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_0p88: ldo2 {
+ regulator-name = "vreg_l2f_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f_0p88: ldo3 {
+ regulator-name = "vreg_l3f_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "g";
+
+ vdd-l1-supply = <&vreg_s4g_1p3>;
+ vdd-l2-supply = <&vreg_s4g_1p3>;
+ vdd-l3-supply = <&vreg_s4g_1p3>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ vreg_s1g_1p2: smps1 {
+ regulator-name = "vreg_s1g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2g_0p8: smps2 {
+ regulator-name = "vreg_s2g_0p8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3g_0p7: smps3 {
+ regulator-name = "vreg_s3g_0p7";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4g_1p3: smps4 {
+ regulator-name = "vreg_s4g_1p3";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1352000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5g_0p8: smps5 {
+ regulator-name = "vreg_s5g_0p8";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6g_1p8: smps6 {
+ regulator-name = "vreg_s6g_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1g_1p2: ldo1 {
+ regulator-name = "vreg_l1g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3g_1p2: ldo3 {
+ regulator-name = "vreg_l3g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&gpi_dma2 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/sm8550/a740_zap.mbn";
+};
+
+&i2c_master_hub_0 {
+ status = "okay";
+};
+
+&i2c_hub_2 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ spk_amp_l: amplifier@34 {
+ compatible = "awinic,aw88166";
+ reg = <0x34>;
+ #sound-dai-cells = <0>;
+ reset-gpios = <&tlmm 103 GPIO_ACTIVE_LOW>;
+ awinic,audio-channel = <0>;
+ awinic,sync-flag;
+ sound-name-prefix = "SPK_L";
+ };
+
+ spk_amp_r: amplifier@35 {
+ compatible = "awinic,aw88166";
+ reg = <0x35>;
+ #sound-dai-cells = <0>;
+ reset-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>;
+ awinic,audio-channel = <1>;
+ awinic,sync-flag;
+ sound-name-prefix = "SPK_R";
+ };
+};
+
+&iris {
+ status = "okay";
+};
+
+&lpass_tlmm {
+ lpi_i2s3_active: lpi_i2s3-active-state {
+ sck-pins {
+ pins = "gpio12";
+ function = "i2s3_clk";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+
+ ws-pins {
+ pins = "gpio13";
+ function = "i2s3_ws";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+
+ data0-pins {
+ pins = "gpio17";
+ function = "i2s3_data";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+
+ data1-pins {
+ pins = "gpio18";
+ function = "i2s3_data";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&lpass_vamacro {
+ qcom,dmic-sample-rate = <4800000>;
+};
+
+&lpass_wsamacro {
+ status = "disabled";
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dp0 {
+ status = "okay";
+};
+
+&mdss_dsi1 {
+ vdda-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+
+ display_panel: panel@0 {
+ reg = <0>;
+
+ port {
+ panel1_in: endpoint {
+ remote-endpoint = <&mdss_dsi1_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi1_out {
+ remote-endpoint = <&panel1_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi1_phy {
+ vdds-supply = <&vreg_l1e_0p88>;
+
+ status = "okay";
+};
+
+&pcie0 {
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcieport0 {
+ wifi@0 {
+ compatible = "pci17cb,1107";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+ vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+ vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+ };
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l1e_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&pm8550_gpios {
+ fan_pwm_active: fan-pwm-active-state {
+ pins = "gpio8";
+ function = "func1";
+ input-disable;
+ output-enable;
+ output-low;
+ bias-disable;
+ power-source = <1>;
+ };
+
+ sdc2_card_det_n: sdc2-card-det-n-state {
+ pins = "gpio12";
+ function = "normal";
+ input-enable;
+ output-disable;
+ bias-pull-up;
+ power-source = <1>;
+ };
+
+ volume_up_n: volume-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&pm8550_pwm {
+ status = "okay";
+
+ pm8550_multi_led: multi-led {
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_STATUS;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@3 {
+ reg = <3>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+};
+
+&pm8550b_eusb2_repeater {
+ qcom,tune-usb2-disc-thres = /bits/ 8 <0x6>;
+ qcom,tune-usb2-amplitude = /bits/ 8 <0xb>;
+ qcom,tune-usb2-preem = /bits/ 8 <0x3>;
+ vdd18-supply = <&vreg_l15b_1p8>;
+ vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&pmk8550_gpios {
+ pmk8550_sleep_clk: sleep-clk-state {
+ pins = "gpio3";
+ function = "func1";
+ input-disable;
+ output-enable;
+ bias-disable;
+ power-source = <0>;
+ };
+
+ pwm_backlight_default: pwm-backlight-default-state {
+ pins = "gpio5";
+ function = "func3";
+ input-disable;
+ output-low;
+ output-enable;
+ bias-disable;
+ power-source = <0>;
+ qcom,drive-strength = <2>;
+ };
+};
+
+&pmk8550_rtc {
+ nvmem-cells = <&rtc_offset>;
+ nvmem-cell-names = "offset";
+};
+
+&pmk8550_sdam_2 {
+ rtc_offset: rtc-offset@bc {
+ reg = <0xbc 0x4>;
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/sm8550/ayntec/cdsp.mbn",
+ "qcom/sm8550/ayntec/cdsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&sdhc_2 {
+ cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&sdc2_default &sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>;
+ pinctrl-names = "default", "sleep";
+ vmmc-supply = <&vreg_l9b_2p9>;
+ vqmmc-supply = <&vreg_l8b_1p8>;
+ no-sdio;
+ no-mmc;
+
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32764>;
+};
+
+&swr1 {
+ status = "okay";
+
+ wcd_rx: codec@0,4 {
+ compatible = "sdw20217010d00";
+ reg = <0 4>;
+ qcom,rx-port-mapping = <1 2 3 4 5>;
+ };
+};
+
+&swr2 {
+ status = "okay";
+
+ wcd_tx: codec@0,3 {
+ compatible = "sdw20217010d00";
+ reg = <0 3>;
+ qcom,tx-port-mapping = <2 2 3 4>;
+ };
+};
+
+&tlmm {
+ gpio-reserved-ranges = <32 8>;
+
+ mcu_en_active: mcu-en-active-state {
+ pins = "gpio12";
+ function = "gpio";
+ bias-pull-down;
+ };
+
+ fan_int: fan-int-state {
+ pins = "gpio13";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ ts_s_rst_default: ts-s-rst-default-state {
+ pins = "gpio14";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ ts_s_rst_sleep: ts-s-rst-sleep-state {
+ pins = "gpio14";
+ function = "gpio";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
+ ts_s_int_default: ts-s-int-default-state {
+ pins = "gpio15";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ ts_s_int_sleep: ts-s-int-sleep-state {
+ pins = "gpio15";
+ function = "gpio";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
+ ts_p_rst_default: ts-p-rst-default-state {
+ pins = "gpio24";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ ts_p_rst_sleep: ts-p-rst-sleep-state {
+ pins = "gpio24";
+ function = "gpio";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
+ ts_p_int_default: ts-p-int-default-state {
+ pins = "gpio25";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ ts_p_int_sleep: ts-p-int-sleep-state {
+ pins = "gpio25";
+ function = "gpio";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
+ wlan_en: wlan-en-state {
+ pins = "gpio80";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+
+ bt_default: bt-default-state {
+ bt-en-pins {
+ pins = "gpio81";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ sw-ctrl-pins {
+ pins = "gpio82";
+ function = "gpio";
+ bias-pull-down;
+ };
+ };
+
+ dsi_p_te_active: dsi-p-te-active-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ dsi_p_te_suspend: dsi-s-te-suspend-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ dsi_s_te_active: dsi-s-te-active-state {
+ pins = "gpio87";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ dsi_s_te_suspend: dsi-s-te-suspend-state {
+ pins = "gpio87";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wcd_default: wcd-reset-n-active-state {
+ pins = "gpio108";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+
+ fan_pwr_active: fan-pwr-active-state {
+ pins = "gpio109";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+
+ dsi_p_rst_active: dsi-p-rst-active-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ dsi_p_rst_suspend: dsi-p-rst-suspend-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ dsi_s_rst_active: dsi-s-rst-active-state {
+ pins = "gpio137";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ dsi_s_rst_suspend: dsi-s-rst-suspend-state {
+ pins = "gpio137";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ usb0_sbu_default: usb0-sbu-state {
+ oe-n-pins {
+ pins = "gpio140";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <16>;
+ output-high;
+ };
+
+ sel-pins {
+ pins = "gpio141";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <16>;
+ };
+ };
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&uart14 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,wcn7850-bt";
+
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+
+ max-speed = <3200000>;
+ };
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l1g_1p2>;
+ vccq-max-microamp = <1200000>;
+ vdd-hba-supply = <&vreg_l3g_1p2>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1d_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_hsphy {
+ phys = <&pm8550b_eusb2_repeater>;
+
+ vdd-supply = <&vreg_l1e_0p88>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l3f_0p88>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss_in>;
+};
+
+&xo_board {
+ clock-frequency = <76800000>;
+};
--
2.53.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v5 3/6] arm64: dts: qcom: Add AYN QCS8550 Common
2026-04-08 19:41 ` [PATCH v5 3/6] arm64: dts: qcom: Add AYN QCS8550 Common Aaron Kling via B4 Relay
@ 2026-04-24 12:11 ` Konrad Dybcio
2026-04-26 22:01 ` Aaron Kling
0 siblings, 1 reply; 12+ messages in thread
From: Konrad Dybcio @ 2026-04-24 12:11 UTC (permalink / raw)
To: webgeek1234, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Teguh Sobirin
On 4/8/26 9:41 PM, Aaron Kling via B4 Relay wrote:
> From: Teguh Sobirin <teguh@sobir.in>
>
> This contains everything common between the AYN QCS8550 devices. It will
> be included by device specific dts'.
>
> Signed-off-by: Teguh Sobirin <teguh@sobir.in>
> Co-developed-by: Aaron Kling <webgeek1234@gmail.com>
> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> ---
[...]
> + // The tzlog label is required by ABL to apply a dtbo, but it can be on any node
I don't know if the policy changed, but I think C-style (/* Foo */)
comments are still preferred
[...]
> + // The arch_timer label is unused here, but is required by ABL to apply a dtbo
> + arch_timer: timer { };
ditto
[...]
> +&pm8550_gpios {
> + fan_pwm_active: fan-pwm-active-state {
> + pins = "gpio8";
> + function = "func1";
> + input-disable;
> + output-enable;
> + output-low;
Looks like this should be a regulator then, probably?
[...]
> + wcd_default: wcd-reset-n-active-state {
> + pins = "gpio108";
> + function = "gpio";
> + drive-strength = <16>;
> + bias-disable;
> + output-low;
no need for this property
> + };
> +
> + fan_pwr_active: fan-pwr-active-state {
> + pins = "gpio109";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + output-low;
likewise, especially since it's the opposite of the active state
defined in the vreg node
[...]
> + usb0_sbu_default: usb0-sbu-state {
> + oe-n-pins {
> + pins = "gpio140";
> + function = "gpio";
> + bias-disable;
> + drive-strength = <16>;
> + output-high;
This is probably not required too.. unless there's a hw bug?
fwiw 16 mA is a very high drive-strength - does this come from vendor
sources?
Konrad
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v5 3/6] arm64: dts: qcom: Add AYN QCS8550 Common
2026-04-24 12:11 ` Konrad Dybcio
@ 2026-04-26 22:01 ` Aaron Kling
2026-04-27 14:45 ` Konrad Dybcio
0 siblings, 1 reply; 12+ messages in thread
From: Aaron Kling @ 2026-04-26 22:01 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Teguh Sobirin
On Fri, Apr 24, 2026 at 7:11 AM Konrad Dybcio
<konrad.dybcio@oss.qualcomm.com> wrote:
>
> On 4/8/26 9:41 PM, Aaron Kling via B4 Relay wrote:
> > From: Teguh Sobirin <teguh@sobir.in>
> >
> > This contains everything common between the AYN QCS8550 devices. It will
> > be included by device specific dts'.
> >
> > Signed-off-by: Teguh Sobirin <teguh@sobir.in>
> > Co-developed-by: Aaron Kling <webgeek1234@gmail.com>
> > Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> > ---
>
> [...]
>
> > + // The tzlog label is required by ABL to apply a dtbo, but it can be on any node
>
> I don't know if the policy changed, but I think C-style (/* Foo */)
> comments are still preferred
Ack
> [...]
>
>
> > + // The arch_timer label is unused here, but is required by ABL to apply a dtbo
> > + arch_timer: timer { };
>
> ditto
Ack
> [...]
>
> > +&pm8550_gpios {
> > + fan_pwm_active: fan-pwm-active-state {
> > + pins = "gpio8";
> > + function = "func1";
> > + input-disable;
> > + output-enable;
> > + output-low;
>
> Looks like this should be a regulator then, probably?
Mmm, what would it be tied to, then? The fan already has a reg. I
presume just modeling it as an always on reg tied to nothing is
undesirable. I also have no idea what the voltage would be.
> [...]
>
> > + wcd_default: wcd-reset-n-active-state {
> > + pins = "gpio108";
> > + function = "gpio";
> > + drive-strength = <16>;
> > + bias-disable;
> > + output-low;
>
> no need for this property
I'll start with saying that I know basically nothing about qcom
hardware design and what the average pinmuxing layout looks like. But
I do note that a lot of existing devices have this exact same node,
for example the sm8550 hdk [0]. Is there something that makes these
devices different? Or is this unnecessary everywhere?
> > + };
> > +
> > + fan_pwr_active: fan-pwr-active-state {
> > + pins = "gpio109";
> > + function = "gpio";
> > + drive-strength = <2>;
> > + bias-disable;
> > + output-low;
>
> likewise, especially since it's the opposite of the active state
> defined in the vreg node
Ack, this one makes sense since the fan power sequence will set stuff
as necessary.
> [...]
>
> > + usb0_sbu_default: usb0-sbu-state {
> > + oe-n-pins {
> > + pins = "gpio140";
> > + function = "gpio";
> > + bias-disable;
> > + drive-strength = <16>;
> > + output-high;
>
> This is probably not required too.. unless there's a hw bug?
>
> fwiw 16 mA is a very high drive-strength - does this come from vendor
> sources?
I do not see any pinmux for gpio140 in the downstream dt or anything
matching pi3usb102 at all, I'm not sure how it's handled there. The
original source of this dt was written before there was a public gpl
code release from AYN. I do see other qcom users of the pi3usb102
doing similar however, for example the sc8280xp crd [1]. So I've got
the same question as above: is there something different here, or is
it possible other existing copies of this are also wrong?
Aaron
[0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/qcom/sm8550-hdk.dts?h=v7.0#n1302
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts?h=v7.0#n1175
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v5 3/6] arm64: dts: qcom: Add AYN QCS8550 Common
2026-04-26 22:01 ` Aaron Kling
@ 2026-04-27 14:45 ` Konrad Dybcio
2026-04-27 17:32 ` Aaron Kling
0 siblings, 1 reply; 12+ messages in thread
From: Konrad Dybcio @ 2026-04-27 14:45 UTC (permalink / raw)
To: Aaron Kling
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Teguh Sobirin
On 4/27/26 12:01 AM, Aaron Kling wrote:
> On Fri, Apr 24, 2026 at 7:11 AM Konrad Dybcio
> <konrad.dybcio@oss.qualcomm.com> wrote:
>>
>> On 4/8/26 9:41 PM, Aaron Kling via B4 Relay wrote:
>>> From: Teguh Sobirin <teguh@sobir.in>
>>>
>>> This contains everything common between the AYN QCS8550 devices. It will
>>> be included by device specific dts'.
>>>
>>> Signed-off-by: Teguh Sobirin <teguh@sobir.in>
>>> Co-developed-by: Aaron Kling <webgeek1234@gmail.com>
>>> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
>>> ---
[...]
>>> +&pm8550_gpios {
>>> + fan_pwm_active: fan-pwm-active-state {
>>> + pins = "gpio8";
>>> + function = "func1";
>>> + input-disable;
>>> + output-enable;
>>> + output-low;
>>
>> Looks like this should be a regulator then, probably?
>
> Mmm, what would it be tied to, then? The fan already has a reg. I
> presume just modeling it as an always on reg tied to nothing is
> undesirable. I also have no idea what the voltage would be.
Or maybe it's some sort of reset/enable GPIO. Or an enable pin to
whatever feeds into VDD_FAN_5V0. It's hard to tell indeed.
>
>> [...]
>>
>>> + wcd_default: wcd-reset-n-active-state {
>>> + pins = "gpio108";
>>> + function = "gpio";
>>> + drive-strength = <16>;
>>> + bias-disable;
>>> + output-low;
>>
>> no need for this property
>
> I'll start with saying that I know basically nothing about qcom
> hardware design and what the average pinmuxing layout looks like. But
> I do note that a lot of existing devices have this exact same node,
> for example the sm8550 hdk [0]. Is there something that makes these
> devices different? Or is this unnecessary everywhere?
That's my understanding.
[...]
>>> + usb0_sbu_default: usb0-sbu-state {
>>> + oe-n-pins {
>>> + pins = "gpio140";
>>> + function = "gpio";
>>> + bias-disable;
>>> + drive-strength = <16>;
>>> + output-high;
>>
>> This is probably not required too.. unless there's a hw bug?
>>
>> fwiw 16 mA is a very high drive-strength - does this come from vendor
>> sources?
>
> I do not see any pinmux for gpio140 in the downstream dt or anything
> matching pi3usb102 at all, I'm not sure how it's handled there. The
> original source of this dt was written before there was a public gpl
> code release from AYN. I do see other qcom users of the pi3usb102
> doing similar however, for example the sc8280xp crd [1]. So I've got
> the same question as above: is there something different here, or is
> it possible other existing copies of this are also wrong?
You can retrieve the settings from your device at runtime,
/sys/kernel/debug/gpio will read back the hw settings
As for the CRD, I don't know. It may as well be board-specific.
Konrad
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v5 3/6] arm64: dts: qcom: Add AYN QCS8550 Common
2026-04-27 14:45 ` Konrad Dybcio
@ 2026-04-27 17:32 ` Aaron Kling
0 siblings, 0 replies; 12+ messages in thread
From: Aaron Kling @ 2026-04-27 17:32 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Teguh Sobirin
On Mon, Apr 27, 2026 at 9:45 AM Konrad Dybcio
<konrad.dybcio@oss.qualcomm.com> wrote:
>
> On 4/27/26 12:01 AM, Aaron Kling wrote:
> > On Fri, Apr 24, 2026 at 7:11 AM Konrad Dybcio
> > <konrad.dybcio@oss.qualcomm.com> wrote:
> >>
> >> On 4/8/26 9:41 PM, Aaron Kling via B4 Relay wrote:
> >>> From: Teguh Sobirin <teguh@sobir.in>
> >>>
> >>> This contains everything common between the AYN QCS8550 devices. It will
> >>> be included by device specific dts'.
> >>>
> >>> Signed-off-by: Teguh Sobirin <teguh@sobir.in>
> >>> Co-developed-by: Aaron Kling <webgeek1234@gmail.com>
> >>> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> >>> ---
>
> [...]
> >>> +&pm8550_gpios {
> >>> + fan_pwm_active: fan-pwm-active-state {
> >>> + pins = "gpio8";
> >>> + function = "func1";
> >>> + input-disable;
> >>> + output-enable;
> >>> + output-low;
> >>
> >> Looks like this should be a regulator then, probably?
> >
> > Mmm, what would it be tied to, then? The fan already has a reg. I
> > presume just modeling it as an always on reg tied to nothing is
> > undesirable. I also have no idea what the voltage would be.
>
> Or maybe it's some sort of reset/enable GPIO. Or an enable pin to
> whatever feeds into VDD_FAN_5V0. It's hard to tell indeed.
Talking to someone working on the downstream kernel for these devices,
the purpose of this is to set the pin to 'func1' or pwm4 output. It's
not a regulator or reset or something that needs otherwise modeled.
> >
> >> [...]
> >>
> >>> + wcd_default: wcd-reset-n-active-state {
> >>> + pins = "gpio108";
> >>> + function = "gpio";
> >>> + drive-strength = <16>;
> >>> + bias-disable;
> >>> + output-low;
> >>
> >> no need for this property
> >
> > I'll start with saying that I know basically nothing about qcom
> > hardware design and what the average pinmuxing layout looks like. But
> > I do note that a lot of existing devices have this exact same node,
> > for example the sm8550 hdk [0]. Is there something that makes these
> > devices different? Or is this unnecessary everywhere?
>
> That's my understanding.
>
> [...]
>
> >>> + usb0_sbu_default: usb0-sbu-state {
> >>> + oe-n-pins {
> >>> + pins = "gpio140";
> >>> + function = "gpio";
> >>> + bias-disable;
> >>> + drive-strength = <16>;
> >>> + output-high;
> >>
> >> This is probably not required too.. unless there's a hw bug?
> >>
> >> fwiw 16 mA is a very high drive-strength - does this come from vendor
> >> sources?
> >
> > I do not see any pinmux for gpio140 in the downstream dt or anything
> > matching pi3usb102 at all, I'm not sure how it's handled there. The
> > original source of this dt was written before there was a public gpl
> > code release from AYN. I do see other qcom users of the pi3usb102
> > doing similar however, for example the sc8280xp crd [1]. So I've got
> > the same question as above: is there something different here, or is
> > it possible other existing copies of this are also wrong?
>
> You can retrieve the settings from your device at runtime,
> /sys/kernel/debug/gpio will read back the hw settings
>
> As for the CRD, I don't know. It may as well be board-specific.
I got pointed in the right direction to see this on downstream. The
active drive strength on gpio140/141 is 8. Does this seem more
reasonable?
Aaron
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v5 4/6] arm64: dts: qcom: Add AYN Odin 2 Mini
2026-04-08 19:41 [PATCH v5 0/6] arm64: dts: qcom: Support AYN QCS8550 Devices Aaron Kling via B4 Relay
` (2 preceding siblings ...)
2026-04-08 19:41 ` [PATCH v5 3/6] arm64: dts: qcom: Add AYN QCS8550 Common Aaron Kling via B4 Relay
@ 2026-04-08 19:41 ` Aaron Kling via B4 Relay
2026-04-08 19:41 ` [PATCH v5 5/6] arm64: dts: qcom: Add AYN Odin 2 Portal Aaron Kling via B4 Relay
2026-04-08 19:41 ` [PATCH v5 6/6] arm64: dts: qcom: Add AYN Thor Aaron Kling via B4 Relay
5 siblings, 0 replies; 12+ messages in thread
From: Aaron Kling via B4 Relay @ 2026-04-08 19:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Aaron Kling,
Teguh Sobirin, Konrad Dybcio
From: Teguh Sobirin <teguh@sobir.in>
The AYN Odin 2 Mini is a high-performance Android-based handheld gaming
console powered by the Qualcomm Snapdragon 8 Gen 2 processor featuring a
5-inch mini-led touchscreen.
Signed-off-by: Teguh Sobirin <teguh@sobir.in>
Co-developed-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/qcs8550-ayntec-odin2mini.dts | 44 ++++++++++++++++++++++
2 files changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 4ba8e730641949..aceb84a060f80e 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -184,6 +184,7 @@ qcs8300-ride-el2-dtbs := qcs8300-ride.dtb monaco-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-el2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qcs8550-ayntec-odin2mini.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayntec-odin2mini.dts b/arch/arm64/boot/dts/qcom/qcs8550-ayntec-odin2mini.dts
new file mode 100644
index 00000000000000..cc894bdd0c9020
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-ayntec-odin2mini.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Teguh Sobirin.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "qcs8550-ayntec-common.dtsi"
+
+&{/} {
+ model = "AYN Odin 2 Mini";
+ compatible = "ayntec,odin2mini", "qcom,qcs8550", "qcom,sm8550";
+
+ vdd_disp_2v8: vdd-disp-2v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_disp_2v8";
+
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ gpio = <&tlmm 142 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+/* There is an hdmi bridge on i2c_hub_0@48, but it is not currently supported */
+
+&remoteproc_adsp {
+ firmware-name = "qcom/sm8550/ayntec/odin2mini/adsp.mbn",
+ "qcom/sm8550/ayntec/odin2mini/adsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&spk_amp_l {
+ firmware-name = "qcom/sm8550/ayntec/odin2mini/aw883xx_acf.bin";
+};
+
+&spk_amp_r {
+ firmware-name = "qcom/sm8550/ayntec/odin2mini/aw883xx_acf.bin";
+};
+
--
2.53.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v5 5/6] arm64: dts: qcom: Add AYN Odin 2 Portal
2026-04-08 19:41 [PATCH v5 0/6] arm64: dts: qcom: Support AYN QCS8550 Devices Aaron Kling via B4 Relay
` (3 preceding siblings ...)
2026-04-08 19:41 ` [PATCH v5 4/6] arm64: dts: qcom: Add AYN Odin 2 Mini Aaron Kling via B4 Relay
@ 2026-04-08 19:41 ` Aaron Kling via B4 Relay
2026-04-08 19:41 ` [PATCH v5 6/6] arm64: dts: qcom: Add AYN Thor Aaron Kling via B4 Relay
5 siblings, 0 replies; 12+ messages in thread
From: Aaron Kling via B4 Relay @ 2026-04-08 19:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Aaron Kling,
Teguh Sobirin, Konrad Dybcio
From: Teguh Sobirin <teguh@sobir.in>
The AYN Odin 2 Portal is a high-performance Android-based handheld gaming
console powered by the Qualcomm Snapdragon 8 Gen 2 processor featuring a
7-inch OLED touchscreen.
Signed-off-by: Teguh Sobirin <teguh@sobir.in>
Co-developed-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/qcs8550-ayntec-odin2portal.dts | 84 ++++++++++++++++++++++
2 files changed, 85 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index aceb84a060f80e..6bfc4554580bd5 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -185,6 +185,7 @@ qcs8300-ride-el2-dtbs := qcs8300-ride.dtb monaco-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-el2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-ayntec-odin2mini.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qcs8550-ayntec-odin2portal.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayntec-odin2portal.dts b/arch/arm64/boot/dts/qcom/qcs8550-ayntec-odin2portal.dts
new file mode 100644
index 00000000000000..bd6ba0ab941d33
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-ayntec-odin2portal.dts
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Teguh Sobirin.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "qcs8550-ayntec-common.dtsi"
+
+&{/} {
+ model = "AYN Odin 2 Portal";
+ compatible = "ayntec,odin2portal", "qcom,qcs8550", "qcom,sm8550";
+
+ vdd_bl_5v0: vdd-bl-5v0-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_bl_5v0";
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&tlmm 52 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_disp_2v8: vdd-disp-2v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_disp_2v8";
+
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ gpio = <&tlmm 142 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen@38 {
+ compatible = "focaltech,ft5426";
+ reg = <0x38>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+
+ reset-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l14b_3p2>;
+ iovcc-supply = <&vreg_l12b_1p8>;
+
+ pinctrl-0 = <&ts_p_rst_default &ts_p_int_default>;
+ pinctrl-1 = <&ts_p_rst_sleep &ts_p_int_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ touchscreen-size-x = <1080>;
+ touchscreen-size-y = <1920>;
+ touchscreen-swapped-x-y;
+ touchscreen-inverted-y;
+ };
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/sm8550/ayntec/odin2portal/adsp.mbn",
+ "qcom/sm8550/ayntec/odin2portal/adsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&spk_amp_l {
+ firmware-name = "qcom/sm8550/ayntec/odin2portal/aw883xx_acf.bin";
+};
+
+&spk_amp_r {
+ firmware-name = "qcom/sm8550/ayntec/odin2portal/aw883xx_acf.bin";
+};
+
--
2.53.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v5 6/6] arm64: dts: qcom: Add AYN Thor
2026-04-08 19:41 [PATCH v5 0/6] arm64: dts: qcom: Support AYN QCS8550 Devices Aaron Kling via B4 Relay
` (4 preceding siblings ...)
2026-04-08 19:41 ` [PATCH v5 5/6] arm64: dts: qcom: Add AYN Odin 2 Portal Aaron Kling via B4 Relay
@ 2026-04-08 19:41 ` Aaron Kling via B4 Relay
2026-04-24 12:06 ` Konrad Dybcio
5 siblings, 1 reply; 12+ messages in thread
From: Aaron Kling via B4 Relay @ 2026-04-08 19:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Aaron Kling,
Teguh Sobirin
From: Teguh Sobirin <teguh@sobir.in>
The AYN Thor is a high-performance Android-based handheld gaming console
powered by the Qualcomm Snapdragon 8 Gen 2 processor featuring dual
AMOLED touchscreens.
Signed-off-by: Teguh Sobirin <teguh@sobir.in>
Co-developed-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/qcs8550-ayntec-thor.dts | 227 +++++++++++++++++++++++
2 files changed, 228 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 6bfc4554580bd5..6feecd62e01546 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -186,6 +186,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-el2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-ayntec-odin2mini.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-ayntec-odin2portal.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qcs8550-ayntec-thor.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayntec-thor.dts b/arch/arm64/boot/dts/qcom/qcs8550-ayntec-thor.dts
new file mode 100644
index 00000000000000..641146a9a7798e
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-ayntec-thor.dts
@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Teguh Sobirin.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "qcs8550-ayntec-common.dtsi"
+
+&{/} {
+ model = "AYN Thor";
+ compatible = "ayntec,thor", "qcom,qcs8550", "qcom,sm8550";
+
+ vdd_bl_5v0: vdd-bl-5v0-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_bl_5v0";
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&tlmm 52 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_disp_1v8: vdd-disp-1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_disp_1v8";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_disp1_2v8: vdd-disp1-2v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_disp1_2v8";
+
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ gpio = <&tlmm 142 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_disp2_2v8: vdd-disp2-2v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_disp2_2v8";
+
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ gpio = <&tlmm 143 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_ts_3v0: vdd-ts-3v0-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_ts_3v0";
+
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+
+ gpio = <&tlmm 144 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vdd_ts_1v8: vdd-ts-1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_ts_1v8";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&gpio_keys {
+ pinctrl-0 = <&volume_up_n &key_ayn_n>;
+
+ key-ayn {
+ label = "AYN Key";
+ debounce-interval = <15>;
+ gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_F24>;
+ linux,can-disable;
+ };
+
+ switch-lid {
+ label = "Hall Lid Sensor";
+ gpios = <&tlmm 17 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ linux,can-disable;
+ wakeup-source;
+ };
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen@38 {
+ compatible = "focaltech,ft5426";
+ reg = <0x38>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+
+ reset-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l14b_3p2>;
+ iovcc-supply = <&vreg_l12b_1p8>;
+
+ pinctrl-0 = <&ts_p_rst_default &ts_p_int_default>;
+ pinctrl-1 = <&ts_p_rst_sleep &ts_p_int_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ touchscreen-size-x = <1080>;
+ touchscreen-size-y = <1920>;
+ touchscreen-swapped-x-y;
+ touchscreen-inverted-x;
+ };
+};
+
+&i2c_hub_3 {
+ clock-frequency = <100000>;
+
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen@38 {
+ compatible = "focaltech,ft5452";
+ reg = <0x38>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
+
+ reset-gpios = <&tlmm 14 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vdd_ts_3v0>;
+ iovcc-supply = <&vdd_ts_1v8>;
+
+ pinctrl-0 = <&ts_s_rst_default &ts_s_int_default>;
+ pinctrl-1 = <&ts_s_rst_sleep &ts_s_int_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ touchscreen-size-x = <1080>;
+ touchscreen-size-y = <1240>;
+ touchscreen-swapped-x-y;
+ touchscreen-inverted-x;
+ };
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel@0 {
+ reg = <0>;
+
+ port {
+ panel0_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <&panel0_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vreg_l1e_0p88>;
+
+ status = "okay";
+};
+
+&mdss_dsi1_out {
+ qcom,te-source = "mdp_vsync_s";
+};
+
+&pm8550_multi_led {
+ status = "disabled";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/sm8550/ayntec/thor/adsp.mbn",
+ "qcom/sm8550/ayntec/thor/adsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&spk_amp_l {
+ firmware-name = "qcom/sm8550/ayntec/thor/aw883xx_acf.bin";
+};
+
+&spk_amp_r {
+ firmware-name = "qcom/sm8550/ayntec/thor/aw883xx_acf.bin";
+};
+
+&tlmm {
+ key_ayn_n: key-ayn-n-state {
+ pins = "gpio41";
+ function = "gpio";
+ bias-pull-up;
+ output-disable;
+ };
+};
--
2.53.0
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v5 6/6] arm64: dts: qcom: Add AYN Thor
2026-04-08 19:41 ` [PATCH v5 6/6] arm64: dts: qcom: Add AYN Thor Aaron Kling via B4 Relay
@ 2026-04-24 12:06 ` Konrad Dybcio
0 siblings, 0 replies; 12+ messages in thread
From: Konrad Dybcio @ 2026-04-24 12:06 UTC (permalink / raw)
To: webgeek1234, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Teguh Sobirin
On 4/8/26 9:41 PM, Aaron Kling via B4 Relay wrote:
> From: Teguh Sobirin <teguh@sobir.in>
>
> The AYN Thor is a high-performance Android-based handheld gaming console
> powered by the Qualcomm Snapdragon 8 Gen 2 processor featuring dual
> AMOLED touchscreens.
>
> Signed-off-by: Teguh Sobirin <teguh@sobir.in>
> Co-developed-by: Aaron Kling <webgeek1234@gmail.com>
> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
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