[PATCH v2 0/2] CQE support for cadence eMMC host controller

[PATCH v2 0/2] CQE support for cadence eMMC host controller

[Rohan Joshi via B4 Relay]

Hi,

This series adds CQE (Command Queue Engine) support for cadence
eMMC host controller. The Cadence controller can support CQE which
is determined by reading a non standard capability register.
Updates to devicetree are also made to identify CQE register space
which may be used by the driver.

Signed-off-by: Rohan Joshi <rohan1sj@cadence.com>
---
Changes in v2:
- Use dev_err_probe() for error messages when in probe path
- Updated commit messages as per subsystem naming conventions
- Select MMC_CQHCI in Kconfig for MMC_SDHCI_CADENCE
- Drop new dt-binding example and corrected existing one
- Link to v1: https://patch.msgid.link/20260407-cdns_sdhci_cqe-support-v1-0-13efc0810631@cadence.com

---
Rohan Joshi (2):
      dt-bindings: mmc: cdns,sdhci: Add CQE support
      mmc: sdhci-cadence: add CQE support

 .../devicetree/bindings/mmc/cdns,sdhci.yaml        | 41 +++++++---------------
 drivers/mmc/host/Kconfig                           |  1 +
 drivers/mmc/host/sdhci-cadence.c                   | 13 +++----
 3 files changed, 17 insertions(+), 38 deletions(-)
---
base-commit: 6d32b7db25329b4492f35a79fed6b1eef48959d2
change-id: 20260505-cdns_sdhci_cqe-support-388542fced5e

Best regards,
--  
Rohan Joshi <rohan1sj@cadence.com>

[PATCH v2 1/2] dt-bindings: mmc: cdns,sdhci: Add CQE support

[Rohan Joshi via B4 Relay]

From: Rohan Joshi <rohan1sj@cadence.com>

Cadence host controller can support CQE. Add optional CQE
register space and reg-names property to cdns sdhci binding

Signed-off-by: Rohan Joshi <rohan1sj@cadence.com>
---
 .../devicetree/bindings/mmc/cdns,sdhci.yaml        | 41 +++++++---------------
 1 file changed, 12 insertions(+), 29 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
index 8902e7925eab..79064282fabc 100644
--- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
@@ -26,7 +26,9 @@ properties:
 
   reg-names:
     minItems: 1
-    maxItems: 2
+    items:
+      - const: hc
+      - const: cqhci
 
   interrupts:
     maxItems: 1
@@ -138,22 +140,16 @@ allOf:
           items:
             - description: Host controller registers
             - description: Elba byte-lane enable register for writes
+        reg-names: false
+      required:
+        - resets
     else:
       properties:
         reg:
-          oneOf:
-            - items:
-                - description: Host controller registers
-            - items:
-                - description: Host controller registers
-                - description: CQE (Command Queue Engine) registers
-        reg-names:
-          oneOf:
-            - items:
-                - const: sdhci
-            - items:
-                - const: sdhci
-                - const: cqhci
+          minItems: 1
+          items:
+            - description: Host Controller registers
+            - description: CQE (Command Queuing Engine) registers
 
 unevaluatedProperties: false
 
@@ -161,7 +157,8 @@ examples:
   - |
     emmc: mmc@5a000000 {
         compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
-        reg = <0x5a000000 0x400>;
+        reg = <0x5a000000 0x400>, <0x5a000400 0x060>;
+        reg-names = "hc", "cqhci";
         interrupts = <0 78 4>;
         clocks = <&clk 4>;
         bus-width = <8>;
@@ -170,17 +167,3 @@ examples:
         mmc-hs400-1_8v;
         cdns,phy-dll-delay-sdclk = <0>;
     };
-
-  - |
-    emmc_cqe: mmc@5b000000 {
-        compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
-        reg = <0x5b000000 0x400>, <0x5b000400 0x060>;
-        reg-names = "sdhci", "cqhci";
-        interrupts = <0 79 4>;
-        clocks = <&clk 4>;
-        bus-width = <8>;
-        mmc-ddr-1_8v;
-        mmc-hs200-1_8v;
-        mmc-hs400-1_8v;
-        cdns,phy-dll-delay-sdclk = <0>;
-    };

-- 
2.34.1

[PATCH v2 2/2] mmc: sdhci-cadence: add CQE support

[Rohan Joshi via B4 Relay]

From: Rohan Joshi <rohan1sj@cadence.com>

Add CQE (Command Queuing Engine) support for all platforms
which use sdhci_cdns_ops. Read additional host capability
register to detect CQE presence

Signed-off-by: Rohan Joshi <rohan1sj@cadence.com>
---
 drivers/mmc/host/Kconfig         |  1 +
 drivers/mmc/host/sdhci-cadence.c | 13 ++++---------
 2 files changed, 5 insertions(+), 9 deletions(-)

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 4f060d3e5636..2cc8133e8ef3 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -293,6 +293,7 @@ config MMC_SDHCI_CADENCE
 	depends on MMC_SDHCI_PLTFM
 	depends on OF
 	select MMC_SDHCI_IO_ACCESSORS
+	select MMC_CQHCI
 	help
 	  This selects the Cadence SD/SDIO/eMMC driver.
 
diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
index 14b12272dae9..1aba8c89821b 100644
--- a/drivers/mmc/host/sdhci-cadence.c
+++ b/drivers/mmc/host/sdhci-cadence.c
@@ -40,7 +40,7 @@
 
 /* Host capabilities not covered by the standard capability registers (SRS16-SRS18) */
 #define SDHCI_CDNS_HRS30		0x78	/* Host capabilities */
-#define   SDHCI_CDNS_HRS30_CQE_SUPPORTED	BIT(0)
+#define SDHCI_CDNS_HRS30_CQE_SUPPORTED	BIT(0)
 
 /* Read block gap */
 #define SDHCI_CDNS_HRS37		0x94	/* interface mode select */
@@ -94,7 +94,7 @@ struct sdhci_cdns_priv {
 	void __iomem *ctl_addr;	/* write control */
 	spinlock_t wrlock;	/* write lock */
 	bool enhanced_strobe;
-	bool cqe_support;   /* Command Queuing Engine support */
+	bool cqe_support;	/* Command Queuing Engine support */
 	void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg);
 	struct reset_control *rst_hw;
 	unsigned int nr_phy_params;
@@ -417,16 +417,14 @@ static int sdhci_cdns_cqe_add_host(struct sdhci_host *host, struct platform_devi
 	bool dma64;
 	int ret;
 
-	/* setup SDHCI host first */
 	ret = sdhci_setup_host(host);
-
 	if (ret)
 		return ret;
 
-	/* Init CQE */
 	cq_host = cqhci_pltfm_init(pdev);
 	if (IS_ERR(cq_host)) {
 		ret = PTR_ERR(cq_host);
+		dev_err_probe(&pdev->dev, ret, "cqhci platform init failed\n");
 		goto cleanup;
 	}
 
@@ -438,10 +436,9 @@ static int sdhci_cdns_cqe_add_host(struct sdhci_host *host, struct platform_devi
 
 	host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
 
-	/* Finally initialize CQHCI */
 	ret = cqhci_init(cq_host, host->mmc, dma64);
 	if (ret) {
-		dev_err(mmc_dev(host->mmc), "Failed to initialize CQHCI: %d\n", ret);
+		dev_err_probe(&pdev->dev, ret, "cqhci init failed\n");
 		goto cleanup;
 	}
 
@@ -450,11 +447,9 @@ static int sdhci_cdns_cqe_add_host(struct sdhci_host *host, struct platform_devi
 	if (ret)
 		goto cleanup;
 
-	dev_info(mmc_dev(host->mmc), "CQE init: success\n");
 	return 0;
 
 cleanup:
-	dev_err(mmc_dev(host->mmc), "CQE init: failed for %s\n", mmc_hostname(host->mmc));
 	sdhci_cleanup_host(host);
 	return ret;
 }

-- 
2.34.1

Re: [PATCH v2 1/2] dt-bindings: mmc: cdns,sdhci: Add CQE support

[Krzysztof Kozlowski]

On 06/05/2026 11:04, Rohan Joshi via B4 Relay wrote:
> From: Rohan Joshi <rohan1sj@cadence.com>
> 
> Cadence host controller can support CQE. Add optional CQE
> register space and reg-names property to cdns sdhci binding
> 
> Signed-off-by: Rohan Joshi <rohan1sj@cadence.com>
> ---
>  .../devicetree/bindings/mmc/cdns,sdhci.yaml        | 41 +++++++---------------
>  1 file changed, 12 insertions(+), 29 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> index 8902e7925eab..79064282fabc 100644
> --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> @@ -26,7 +26,9 @@ properties:
>  
>    reg-names:

There are no reg-names in this file.

>      minItems: 1
> -    maxItems: 2
> +    items:
> +      - const: hc
> +      - const: cqhci
>  
>    interrupts:
>      maxItems: 1
> @@ -138,22 +140,16 @@ allOf:
>            items:
>              - description: Host controller registers
>              - description: Elba byte-lane enable register for writes
> +        reg-names: false

Why?

> +      required:
> +        - resets

Why?

>      else:
>        properties:
>          reg:
> -          oneOf:
> -            - items:
> -                - description: Host controller registers
> -            - items:
> -                - description: Host controller registers
> -                - description: CQE (Command Queue Engine) registers
> -        reg-names:
> -          oneOf:
> -            - items:
> -                - const: sdhci
> -            - items:
> -                - const: sdhci
> -                - const: cqhci
> +          minItems: 1
> +          items:
> +            - description: Host Controller registers
> +            - description: CQE (Command Queuing Engine) registers

Why each device has CQE? If each, then why not Pensando?



>  
>  unevaluatedProperties: false
>  
> @@ -161,7 +157,8 @@ examples:
>    - |
>      emmc: mmc@5a000000 {
>          compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
> -        reg = <0x5a000000 0x400>;
> +        reg = <0x5a000000 0x400>, <0x5a000400 0x060>;
> +        reg-names = "hc", "cqhci";
>          interrupts = <0 78 4>;
>          clocks = <&clk 4>;
>          bus-width = <8>;
> @@ -170,17 +167,3 @@ examples:
>          mmc-hs400-1_8v;
>          cdns,phy-dll-delay-sdclk = <0>;
>      };
> -
> -  - |

What are you doing here?


Best regards,
Krzysztof

Re: [PATCH v2 2/2] mmc: sdhci-cadence: add CQE support

[Krzysztof Kozlowski]

On 06/05/2026 11:04, Rohan Joshi via B4 Relay wrote:
> @@ -450,11 +447,9 @@ static int sdhci_cdns_cqe_add_host(struct sdhci_host *host, struct platform_devi
>  	if (ret)
>  		goto cleanup;
>  
> -	dev_info(mmc_dev(host->mmc), "CQE init: success\n");

I don't think you understand how Git works. :(

Best regards,
Krzysztof