From: Bjorn Andersson <andersson@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Luo Jie <quic_luoj@quicinc.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Luo Jie <jie.luo@oss.qualcomm.com>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com,
quic_leiwei@quicinc.com, quic_pavir@quicinc.com,
quic_suruchia@quicinc.com,
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Subject: Re: (subset) [PATCH v2 0/5] Add CMN PLL clock controller support for IPQ5332
Date: Wed, 13 May 2026 14:09:20 -0500 [thread overview]
Message-ID: <177869936432.1496622.9030891427127725229.b4-ty@kernel.org> (raw)
In-Reply-To: <20260106-qcom_ipq5332_cmnpll-v2-0-f9f7e4efbd79@oss.qualcomm.com>
On Tue, 06 Jan 2026 21:35:09 -0800, Luo Jie wrote:
> This patch series adds support for the CMN PLL block on the IPQ5332 SoC.
> The CMN PLL implementation in IPQ5332 is largely similar to that of
> IPQ9574, which is already supported by the driver. The primary difference
> is that the fixed output clocks to PPE from the CMN PLL operate at 200 MHz.
>
> Additionally, IPQ5332 provides a single 50 MHz clock to both UNIPHY (PCS)
> instances, which in turn supply either 25 MHz or 50 MHz to the connected
> Ethernet PHY or switch.
>
> [...]
Applied, thanks!
[1/5] clk: qcom: cmnpll: Account for reference clock divider
commit: 88c543fff756450bcd04ec4560c4440be36c9e75
[3/5] clk: qcom: cmnpll: Add IPQ5332 SoC support
commit: 1dcbf4195a262d57f4da812248cdbbcdc81bf8d8
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
parent reply other threads:[~2026-05-13 19:09 UTC|newest]
Thread overview: expand[flat|nested] mbox.gz Atom feed
[parent not found: <20260106-qcom_ipq5332_cmnpll-v2-0-f9f7e4efbd79@oss.qualcomm.com>]
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