* Re: (subset) [PATCH v2 0/5] Add CMN PLL clock controller support for IPQ5332
[not found] <20260106-qcom_ipq5332_cmnpll-v2-0-f9f7e4efbd79@oss.qualcomm.com>
@ 2026-05-13 19:09 ` Bjorn Andersson
0 siblings, 0 replies; only message in thread
From: Bjorn Andersson @ 2026-05-13 19:09 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Konrad Dybcio, Luo Jie,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Luo Jie
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, quic_kkumarcs,
quic_linchen, quic_leiwei, quic_pavir, quic_suruchia,
Krzysztof Kozlowski
On Tue, 06 Jan 2026 21:35:09 -0800, Luo Jie wrote:
> This patch series adds support for the CMN PLL block on the IPQ5332 SoC.
> The CMN PLL implementation in IPQ5332 is largely similar to that of
> IPQ9574, which is already supported by the driver. The primary difference
> is that the fixed output clocks to PPE from the CMN PLL operate at 200 MHz.
>
> Additionally, IPQ5332 provides a single 50 MHz clock to both UNIPHY (PCS)
> instances, which in turn supply either 25 MHz or 50 MHz to the connected
> Ethernet PHY or switch.
>
> [...]
Applied, thanks!
[1/5] clk: qcom: cmnpll: Account for reference clock divider
commit: 88c543fff756450bcd04ec4560c4440be36c9e75
[3/5] clk: qcom: cmnpll: Add IPQ5332 SoC support
commit: 1dcbf4195a262d57f4da812248cdbbcdc81bf8d8
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
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