[PATCH] dt-bindings: cache: l2c2x0: Add missing power-domains

[PATCH] dt-bindings: cache: l2c2x0: Add missing power-domains

[Geert Uytterhoeven]

On Renesas SH-Mobile and R-Mobile SoCs, the ARM PL310 L2 Cache
Controller is located in a controllable power area.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
This fixes "make dtbs_check":

    arch/arm/boot/dts/renesas/r8a7740-armadillo800eva.dtb: cache-controller@f0100000 (arm,pl310-cache): 'power-domains' does not match any of the regexes: '^pinctrl-[0-9]+$'
	    from schema $id: http://devicetree.org/schemas/cache/l2c2x0.yaml
    arch/arm/boot/dts/renesas/sh73a0-kzm9g.dtb: cache-controller@f0100000 (arm,pl310-cache): 'power-domains' does not match any of the regexes: '^pinctrl-[0-9]+$'
	    from schema $id: http://devicetree.org/schemas/cache/l2c2x0.yaml
---
 Documentation/devicetree/bindings/cache/l2c2x0.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/cache/l2c2x0.yaml b/Documentation/devicetree/bindings/cache/l2c2x0.yaml
index 10c1a900202fc2ed..ee604117ffb3fe74 100644
--- a/Documentation/devicetree/bindings/cache/l2c2x0.yaml
+++ b/Documentation/devicetree/bindings/cache/l2c2x0.yaml
@@ -66,6 +66,9 @@ properties:
   reg:
     maxItems: 1
 
+  power-domains:
+    maxItems: 1
+
   arm,data-latency:
     description: Cycles of latency for Data RAM accesses. Specifies 3 cells of
       read, write and setup latencies. Minimum valid values are 1. Controllers
-- 
2.43.0

Re: [PATCH] dt-bindings: cache: l2c2x0: Add missing power-domains

[Krzysztof Kozlowski]

On Wed, Jun 10, 2026 at 05:29:20PM +0200, Geert Uytterhoeven wrote:
> On Renesas SH-Mobile and R-Mobile SoCs, the ARM PL310 L2 Cache
> Controller is located in a controllable power area.

Interesting... so to turn on L2 cache, OS would need to boot, setup
power domains handling, turn on power domain and then turn on L2 cache?

I understand that bootloader actually handles it, but I really doubt
that it is "controllable".

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH] dt-bindings: cache: l2c2x0: Add missing power-domains

[Geert Uytterhoeven]

Hi Krzysztof,

On Thu, 11 Jun 2026 at 11:28, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> On Wed, Jun 10, 2026 at 05:29:20PM +0200, Geert Uytterhoeven wrote:
> > On Renesas SH-Mobile and R-Mobile SoCs, the ARM PL310 L2 Cache
> > Controller is located in a controllable power area.
>
> Interesting... so to turn on L2 cache, OS would need to boot, setup
> power domains handling, turn on power domain and then turn on L2 cache?

On R-Mobile A1, the L2 cache is even located in the same power area
as the Cortex A9 CPU core ;-)

> I understand that bootloader actually handles it, but I really doubt
> that it is "controllable".

It may also depends on which CPU core is started first.  These SoCs have
both ARM and SH CPU cores, and the SH core can power down all ARM parts.

But hey, DT describes hardware ;-)

> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Thanks!

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH] dt-bindings: cache: l2c2x0: Add missing power-domains

[Rob Herring (Arm)]

On Wed, 10 Jun 2026 17:29:20 +0200, Geert Uytterhoeven wrote:
> On Renesas SH-Mobile and R-Mobile SoCs, the ARM PL310 L2 Cache
> Controller is located in a controllable power area.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> This fixes "make dtbs_check":
> 
>     arch/arm/boot/dts/renesas/r8a7740-armadillo800eva.dtb: cache-controller@f0100000 (arm,pl310-cache): 'power-domains' does not match any of the regexes: '^pinctrl-[0-9]+$'
> 	    from schema $id: http://devicetree.org/schemas/cache/l2c2x0.yaml
>     arch/arm/boot/dts/renesas/sh73a0-kzm9g.dtb: cache-controller@f0100000 (arm,pl310-cache): 'power-domains' does not match any of the regexes: '^pinctrl-[0-9]+$'
> 	    from schema $id: http://devicetree.org/schemas/cache/l2c2x0.yaml
> ---
>  Documentation/devicetree/bindings/cache/l2c2x0.yaml | 3 +++
>  1 file changed, 3 insertions(+)
> 

Applied, thanks!

Re: [PATCH] dt-bindings: cache: l2c2x0: Add missing power-domains

[Conor Dooley]

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On Fri, Jun 12, 2026 at 09:11:42AM -0500, Rob Herring (Arm) wrote:
> 
> On Wed, 10 Jun 2026 17:29:20 +0200, Geert Uytterhoeven wrote:
> > On Renesas SH-Mobile and R-Mobile SoCs, the ARM PL310 L2 Cache
> > Controller is located in a controllable power area.
> > 
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > ---
> > This fixes "make dtbs_check":
> > 
> >     arch/arm/boot/dts/renesas/r8a7740-armadillo800eva.dtb: cache-controller@f0100000 (arm,pl310-cache): 'power-domains' does not match any of the regexes: '^pinctrl-[0-9]+$'
> > 	    from schema $id: http://devicetree.org/schemas/cache/l2c2x0.yaml
> >     arch/arm/boot/dts/renesas/sh73a0-kzm9g.dtb: cache-controller@f0100000 (arm,pl310-cache): 'power-domains' does not match any of the regexes: '^pinctrl-[0-9]+$'
> > 	    from schema $id: http://devicetree.org/schemas/cache/l2c2x0.yaml
> > ---
> >  Documentation/devicetree/bindings/cache/l2c2x0.yaml | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> 
> Applied, thanks!

Thanks Rob, was at an awkward time for me and would've probably sat til
rc1.

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