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From: "Rob Herring (Arm)" <robh@kernel.org>
To: Yu-Chien Peter Lin <peter.lin@sifive.com>
Cc: anup@brainfault.org, guodong@riscstar.com,
	 pincheng.plct@isrc.iscas.ac.cn, alex@ghiti.fr,
	aou@eecs.berkeley.edu,  linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org,  michal.simek@amd.com,
	dave.patel@riscstar.com, pjw@kernel.org,
	 linux-riscv@lists.infradead.org, zhangchunyan@iscas.ac.cn,
	 raymond.mao@riscstar.com, palmer@dabbelt.com,
	greentime.hu@sifive.com,  dfustini@oss.tenstorrent.com,
	luxu.kernel@bytedance.com,  conor+dt@kernel.org,
	akpm@linux-foundation.org, scott@riscstar.com,
	 jim.shu@sifive.com, krzk+dt@kernel.org,
	robin.randhawa@sifive.com,  zong.li@sifive.com,
	pawandeep.oza@oss.qualcomm.com, nick.hu@sifive.com,
	 samuel.holland@sifive.com, darshan.prajapati@einfochips.com,
	 junhui.liu@pigmoral.tech, dlan@kernel.org
Subject: Re: [PATCH v2 2/3] dt-bindings: riscv: Add Worlds per-hart properties
Date: Wed, 29 Jul 2026 13:06:59 -0500	[thread overview]
Message-ID: <178534841698.3259786.10094204605740986474.robh@kernel.org> (raw)
In-Reply-To: <20260729163908.249838-3-peter.lin@sifive.com>


On Thu, 30 Jul 2026 00:39:07 +0800, Yu-Chien Peter Lin wrote:
> Add per-hart DT properties for the RISC-V Worlds architecture:
> riscv,pmwid, riscv,pmwidlist, and riscv,pmlwidlist. These
> platform-defined values are primarily used by M-mode firmware
> to configure World ID CSRs and restrict WID usage across
> privilege levels.
> 
> Also add schema validation rules to enforce valid property
> combinations based on the ISA extensions present.
> 
> Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
> ---
>  .../devicetree/bindings/riscv/cpus.yaml       | 61 +++++++++++++++
>  .../devicetree/bindings/riscv/worlds.yaml     | 77 +++++++++++++++++++
>  2 files changed, 138 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/riscv/worlds.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/cpu/idle-states.example.dtb: cpu@0 (riscv): 'riscv,pmwid' is a required property
	from schema $id: http://devicetree.org/schemas/riscv/cpus.yaml
Documentation/devicetree/bindings/cpu/idle-states.example.dtb: cpu@1 (riscv): 'riscv,pmwid' is a required property
	from schema $id: http://devicetree.org/schemas/riscv/cpus.yaml
Documentation/devicetree/bindings/cpu/idle-states.example.dtb: cpu@10 (riscv): 'riscv,pmwid' is a required property
	from schema $id: http://devicetree.org/schemas/riscv/cpus.yaml
Documentation/devicetree/bindings/cpu/idle-states.example.dtb: cpu@11 (riscv): 'riscv,pmwid' is a required property
	from schema $id: http://devicetree.org/schemas/riscv/cpus.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.kernel.org/project/devicetree/patch/20260729163908.249838-3-peter.lin@sifive.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.


  parent reply	other threads:[~2026-07-29 18:07 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-29 16:39 [PATCH v2 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings Yu-Chien Peter Lin
2026-07-29 16:39 ` [PATCH v2 1/3] dt-bindings: riscv: Add Worlds ISA extensions Yu-Chien Peter Lin
2026-07-29 16:45   ` sashiko-bot
2026-07-29 16:39 ` [PATCH v2 2/3] dt-bindings: riscv: Add Worlds per-hart properties Yu-Chien Peter Lin
2026-07-29 16:52   ` sashiko-bot
2026-07-29 18:06   ` Rob Herring (Arm) [this message]
2026-07-29 16:39 ` [PATCH v2 3/3] dt-bindings: sifive: Add WorldGuard Checker Yu-Chien Peter Lin
2026-07-29 18:07   ` Rob Herring (Arm)

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