Re: [PATCH v2 1/3] dt-bindings: riscv: Add Worlds ISA extensions

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Medium] S-mode extension 'sswid' imposes an invalid schema dependency on M-mode extension 'smwiddeleg', breaking guest VM device trees.
- [Medium] The patch contains 'TBD' placeholders for the ratification commit hashes of the newly added standard extensions.
- [Low] The newly added multi-letter extensions violate the strict alphanumeric sorting requirement.
--

--- Patch [1]: [PATCH v2 1/3] dt-bindings: riscv: Add Worlds ISA extensions ---
commit f77a112e3cec85c24b75fb71cd433146ac340c50
Author: Yu-Chien Peter Lin <peter.lin@sifive.com>

dt-bindings: riscv: Add Worlds ISA extensions

This commit adds device tree bindings for five RISC-V Worlds ISA extensions
that implement World ID tagging for hardware-enforced context isolation. It
also adds checks for extension dependency requirements.

> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 5ffc40d599c02..3fb13b860e701 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -193,12 +193,35 @@ properties:
>              ratified at commit d70011dde6c2 ("Update to ratified state")
>              of riscv-j-extension.
>  
> +        - const: smlwid
> +          description: |
> +            The standard Smlwid extension for M-mode control of lower
> +            privilege World ID via the mlwid CSR as ratified at commit
> +            TBD ("TBD") of riscv-worlds.

[Severity: Medium]
Is this extension fully ratified? 

The description still contains TBD for the ratification commit hashes here and
in the other extensions added by this patch.

Could you update the TBD placeholders with the actual commit hashes if the
extensions are complete?

> +
> +        - const: smlwidlist
> +          description: |
> +            The standard Smlwidlist extension for M-mode control of lower
> +            privilege World IDs via the mlwidlist CSR as ratified at commit
> +            TBD ("TBD") of riscv-worlds.
> +
>          - const: smstateen
>            description: |
>              The standard Smstateen extension for controlling access to CSRs
>              added by other RISC-V extensions in H/S/VS/U/VU modes and as
>              ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
>  
> +        - const: smwiddeleg
> +          description: |
> +            The standard Smwiddeleg extension for M-mode delegation of lower
> +            privilege World ID control to S-mode via the mwiddeleg CSR, as
> +            ratified at commit TBD ("TBD") of riscv-worlds.
> +
> +        - const: smwid

[Severity: Low]
Does this ordering violate the alphanumeric sorting requirement for
multi-letter extensions?

It appears smwiddeleg is placed before smwid, which is alphabetically
incorrect since smwid is a prefix and should come first. 

Also, smlwid and smlwidlist appear to be inserted out of alphanumeric order
compared to the surrounding extensions.

[ ... ]

> @@ -924,6 +953,30 @@ properties:
[ ... ]
> +      # Sswid depends on Smwiddeleg
> +      - if:
> +          contains:
> +            const: sswid
> +        then:
> +          contains:
> +            const: smwiddeleg

[Severity: Medium]
Could this strict dependency cause a regression for guest VM device trees?

This block requires the M-mode smwiddeleg extension to be present whenever
the S-mode sswid extension is declared. In RISC-V systems, hypervisors
typically only expose Supervisor and User mode extensions to guest VMs.

If a valid guest VM device tree contains sswid but omits M-mode capabilities
like smwiddeleg, wouldn't it falsely fail validation?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260729163908.249838-1-peter.lin@sifive.com?part=1