From: Jerome Brunet <jbrunet@baylibre.com>
To: Yu-Chun Lin <eleanor.lin@realtek.com>
Cc: sboyd@kernel.org, bmasney+clk@redhat.com,
jbrunet+clk@baylibre.com, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, p.zabel@pengutronix.de,
cylee12@realtek.com, afaerber@suse.com, jyanchou@realtek.com,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-realtek-soc@lists.infradead.org, james.tai@realtek.com,
cy.huang@realtek.com, stanley_chang@realtek.com,
Brian Masney <bmasney@redhat.com>
Subject: Re: [PATCH v14 04/11] clk: realtek: Introduce common probe()
Date: Tue, 15 Sep 2026 14:26:17 +0200 [thread overview]
Message-ID: <178947517742.448573.7975580808033616494.b4-reply@b4> (raw)
In-Reply-To: <20260901072446.2563145-5-eleanor.lin@realtek.com>
On 2026-09-01 15:24 +0800, Yu-Chun Lin wrote:
> From: Cheng-Yu Lee <cylee12@realtek.com>
>
> Add rtk_clk_probe() to set up the shared regmap, register clock hardware,
> and add the clock provider.
>
> Additionally, if the "#reset-cells" property is present in the device tree,
> it creates and registers an auxiliary device using the provided aux_name.
> This allows the dedicated reset driver to bind to this device, enabling
> both clock and reset drivers to share the same regmap.
>
> Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com>
> Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com>
> Reviewed-by: Brian Masney <bmasney@redhat.com>
> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
> ---
> Changes in v14:
> - Move Reviewed-by tags to the correct position.
> - Use devm_platform_ioremap_resource() + devm_regmap_init_mmio() instead
> of device_node_to_regmap().
> - Drop rtk_clk_remove().
> ---
> MAINTAINERS | 1 +
> drivers/clk/Kconfig | 1 +
> drivers/clk/Makefile | 1 +
> drivers/clk/realtek/Kconfig | 30 ++++++++++
> drivers/clk/realtek/Makefile | 4 ++
> drivers/clk/realtek/clk-rtk-common.c | 82 ++++++++++++++++++++++++++++
> drivers/clk/realtek/clk-rtk-common.h | 37 +++++++++++++
> 7 files changed, 156 insertions(+)
> create mode 100644 drivers/clk/realtek/Kconfig
> create mode 100644 drivers/clk/realtek/Makefile
> create mode 100644 drivers/clk/realtek/clk-rtk-common.c
> create mode 100644 drivers/clk/realtek/clk-rtk-common.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index a752551f32f9..e55eb1c06119 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -22746,6 +22746,7 @@ M: Cheng-Yu Lee <cylee12@realtek.com>
> M: Yu-Chun Lin <eleanor.lin@realtek.com>
> S: Supported
> F: Documentation/devicetree/bindings/clock/realtek*
> +F: drivers/clk/realtek/*
> F: drivers/reset/realtek/*
> F: include/dt-bindings/clock/realtek*
> F: include/dt-bindings/reset/realtek*
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 1717ce75a907..97ad817457db 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -525,6 +525,7 @@ source "drivers/clk/nuvoton/Kconfig"
> source "drivers/clk/pistachio/Kconfig"
> source "drivers/clk/qcom/Kconfig"
> source "drivers/clk/ralink/Kconfig"
> +source "drivers/clk/realtek/Kconfig"
> source "drivers/clk/renesas/Kconfig"
> source "drivers/clk/rockchip/Kconfig"
> source "drivers/clk/samsung/Kconfig"
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index cc108a75a900..b1aa373e9f84 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -141,6 +141,7 @@ obj-$(CONFIG_COMMON_CLK_PISTACHIO) += pistachio/
> obj-$(CONFIG_COMMON_CLK_PXA) += pxa/
> obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
> obj-y += ralink/
> +obj-$(CONFIG_COMMON_CLK_REALTEK) += realtek/
> obj-y += renesas/
> obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += rockchip/
> obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
> diff --git a/drivers/clk/realtek/Kconfig b/drivers/clk/realtek/Kconfig
> new file mode 100644
> index 000000000000..778f5b4a967a
> --- /dev/null
> +++ b/drivers/clk/realtek/Kconfig
> @@ -0,0 +1,30 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +config COMMON_CLK_REALTEK
> + tristate "Clock driver for Realtek SoCs"
> + depends on ARCH_REALTEK || COMPILE_TEST
> + default ARCH_REALTEK
> + help
> + Enable the common clock framework infrastructure for Realtek
> + system-on-chip platforms.
> +
> + This provides the base support required by individual Realtek
> + clock controller drivers to expose clocks to peripheral devices.
> +
> + If you have a Realtek-based platform, say Y.
> +
> +if COMMON_CLK_REALTEK
> +
> +config RTK_CLK_COMMON
> + tristate "Realtek Clock Common"
> + depends on RESET_CONTROLLER
> + select AUXILIARY_BUS
> + select REGMAP_MMIO
> + select RESET_RTK_COMMON
Is there compile time dependency with reset that I missed ?
The point of the aux bus is to remove such dep
> + help
> + Common helper code shared by Realtek clock controller drivers.
> +
> + This provides utility functions and data structures used by
> + multiple Realtek clock implementations, and include integration
> + with reset controllers where required.
> +
> +endif
> diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile
> new file mode 100644
> index 000000000000..13000ed4ba11
> --- /dev/null
> +++ b/drivers/clk/realtek/Makefile
> @@ -0,0 +1,4 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +obj-$(CONFIG_RTK_CLK_COMMON) += clk-rtk.o
> +
> +clk-rtk-y += clk-rtk-common.o
> diff --git a/drivers/clk/realtek/clk-rtk-common.c b/drivers/clk/realtek/clk-rtk-common.c
> new file mode 100644
> index 000000000000..493f2d5588d0
> --- /dev/null
> +++ b/drivers/clk/realtek/clk-rtk-common.c
> @@ -0,0 +1,82 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2019-2026 Realtek Semiconductor Corporation
> + * Author: Cheng-Yu Lee <cylee12@realtek.com>
> + */
> +
> +#include <linux/auxiliary_bus.h>
> +#include <linux/device.h>
> +#include <linux/export.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include "clk-rtk-common.h"
> +
> +static int rtk_reset_controller_register(struct device *dev, const char *aux_name,
> + struct regmap *map)
> +{
> + struct auxiliary_device *adev;
> +
> + if (!of_property_present(dev->of_node, "#reset-cells"))
> + return 0;
> +
> + if (!aux_name) {
> + dev_err(dev, "DTS requires reset controller, but aux_name is missing\n");
> + return -EINVAL;
> + }
> +
> + adev = devm_auxiliary_device_create(dev, aux_name, (void *)map);
> + if (!adev)
> + return -ENOMEM;
> +
> + return 0;
> +}
> +
> +static const struct regmap_config rtk_clk_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> +};
> +
> +int rtk_clk_probe(struct platform_device *pdev, const struct rtk_clk_desc *desc)
> +{
> + struct device *dev = &pdev->dev;
> + struct regmap *regmap;
> + void __iomem *base;
> + struct clk_hw *hw;
> + int i, ret;
> +
> + base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + regmap = devm_regmap_init_mmio(dev, base, &rtk_clk_regmap_config);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + for (i = 0; i < desc->num_clks; i++)
> + desc->clks[i]->regmap = regmap;
> +
> + for (i = 0; i < desc->clk_data->num; i++) {
> + hw = desc->clk_data->hws[i];
> + if (!hw)
> + continue;
> +
> + ret = devm_clk_hw_register(dev, hw);
> + if (ret)
> + return dev_err_probe(dev, ret, "failed to register hw of clk%d\n", i);
> + }
> +
> + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> + desc->clk_data);
> + if (ret)
> + return dev_err_probe(dev, ret, "failed to add clock provider\n");
> +
> + platform_set_drvdata(pdev, (void *)desc);
> +
> + return rtk_reset_controller_register(dev, desc->aux_name, regmap);
sashiko report on Patch 10 is actually not a prexisting issue. it is here.
Could you address it ?
> +}
> +EXPORT_SYMBOL_NS_GPL(rtk_clk_probe, "CLK_REALTEK");
> +
> +MODULE_DESCRIPTION("Realtek clock infrastructure");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/clk/realtek/clk-rtk-common.h b/drivers/clk/realtek/clk-rtk-common.h
> new file mode 100644
> index 000000000000..de3f23120b53
> --- /dev/null
> +++ b/drivers/clk/realtek/clk-rtk-common.h
> @@ -0,0 +1,37 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2016-2026 Realtek Semiconductor Corporation
> + * Author: Cheng-Yu Lee <cylee12@realtek.com>
> + */
> +
> +#ifndef __CLK_REALTEK_COMMON_H
> +#define __CLK_REALTEK_COMMON_H
> +
> +#include <linux/clk-provider.h>
> +
> +#define __rtk_clk_regmap_hw(_p) ((_p)->hw)
> +
> +struct device;
> +struct platform_device;
> +struct regmap;
> +
> +struct rtk_clk_regmap {
> + struct clk_hw hw;
> + struct regmap *regmap;
> +};
> +
> +struct rtk_clk_desc {
> + struct clk_hw_onecell_data *clk_data;
> + struct rtk_clk_regmap **clks;
> + size_t num_clks;
> + char *aux_name;
> +};
> +
> +static inline struct rtk_clk_regmap *to_rtk_clk_regmap(struct clk_hw *hw)
> +{
> + return container_of(hw, struct rtk_clk_regmap, hw);
> +}
> +
> +int rtk_clk_probe(struct platform_device *pdev, const struct rtk_clk_desc *desc);
> +
> +#endif /* __CLK_REALTEK_COMMON_H */
> --
> 2.43.0
>
>
next prev parent reply other threads:[~2026-09-15 12:26 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-01 7:24 [PATCH v14 00/11] clk / reset: realtek: Add RTD1625 clock and reset support Yu-Chun Lin
2026-09-01 7:24 ` [PATCH v14 01/11] dt-bindings: clock: Add Realtek RTD1625 Clock & Reset Controller Yu-Chun Lin
2026-09-01 7:24 ` [PATCH v14 02/11] reset: Add Realtek basic reset support Yu-Chun Lin
2026-09-01 7:24 ` [PATCH v14 03/11] reset: realtek: Add RTD1625 reset controller driver Yu-Chun Lin
2026-09-01 7:24 ` [PATCH v14 04/11] clk: realtek: Introduce common probe() Yu-Chun Lin
2026-09-15 12:26 ` Jerome Brunet [this message]
2026-09-23 5:40 ` Yu-Chun Lin [林祐君]
2026-09-01 7:24 ` [PATCH v14 05/11] clk: realtek: Add support for phase locked loops (PLLs) Yu-Chun Lin
2026-09-01 7:24 ` [PATCH v14 06/11] clk: realtek: Add support for gate clock Yu-Chun Lin
2026-09-15 12:42 ` Jerome Brunet
2026-09-23 5:41 ` Yu-Chun Lin [林祐君]
2026-09-01 7:24 ` [PATCH v14 07/11] clk: realtek: Add support for mux clock Yu-Chun Lin
2026-09-15 12:53 ` Jerome Brunet
2026-09-23 5:42 ` Yu-Chun Lin [林祐君]
2026-09-01 7:24 ` [PATCH v14 08/11] clk: realtek: Add support for MMC-tuned PLL clocks Yu-Chun Lin
2026-09-01 7:24 ` [PATCH v14 09/11] clk: realtek: Add RTD1625-CRT clock controller driver Yu-Chun Lin
2026-09-15 13:02 ` Jerome Brunet
2026-09-23 5:43 ` Yu-Chun Lin [林祐君]
2026-09-25 9:14 ` Jerome Brunet
2026-09-30 6:17 ` Yu-Chun Lin [林祐君]
2026-09-01 7:24 ` [PATCH v14 10/11] clk: realtek: Add RTD1625-ISO " Yu-Chun Lin
2026-09-01 7:41 ` sashiko-bot
2026-09-01 7:24 ` [PATCH v14 11/11] arm64: dts: realtek: Add clock support for RTD1625 Yu-Chun Lin
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