Re: [PATCH v14 07/11] clk: realtek: Add support for mux clock

[Jerome Brunet <jbrunet@baylibre.com>]

On 2026-09-01 15:24 +0800, Yu-Chun Lin wrote:
> From: Cheng-Yu Lee <cylee12@realtek.com>
> 
> Add a simple regmap-based clk_ops implementation for Realtek mux clocks.
> 
> The implementation supports parent selection and rate determination through
> regmap-backed register access.
> 
> Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com>
> Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com>
> Reviewed-by: Brian Masney <bmasney@redhat.com>
> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
> ---
> Changes in v14:
> - Move Reviewed-by tag to the correct position.
> ---
>  drivers/clk/realtek/Makefile         |  1 +
>  drivers/clk/realtek/clk-regmap-mux.c | 41 ++++++++++++++++++++++++++
>  drivers/clk/realtek/clk-regmap-mux.h | 43 ++++++++++++++++++++++++++++
>  3 files changed, 85 insertions(+)
>  create mode 100644 drivers/clk/realtek/clk-regmap-mux.c
>  create mode 100644 drivers/clk/realtek/clk-regmap-mux.h
> 
> diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile
> index 840aff067b61..217ccaf5644a 100644
> --- a/drivers/clk/realtek/Makefile
> +++ b/drivers/clk/realtek/Makefile
> @@ -4,4 +4,5 @@ obj-$(CONFIG_RTK_CLK_COMMON) += clk-rtk.o
>  clk-rtk-y += clk-rtk-common.o
>  clk-rtk-y += clk-pll.o
>  clk-rtk-y += clk-regmap-gate.o
> +clk-rtk-y += clk-regmap-mux.o
>  clk-rtk-y += freq_table.o
> diff --git a/drivers/clk/realtek/clk-regmap-mux.c b/drivers/clk/realtek/clk-regmap-mux.c
> new file mode 100644
> index 000000000000..1069c95595aa
> --- /dev/null
> +++ b/drivers/clk/realtek/clk-regmap-mux.c
> @@ -0,0 +1,41 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2017-2026 Realtek Semiconductor Corporation
> + * Author: Cheng-Yu Lee <cylee12@realtek.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/export.h>
> +#include <linux/regmap.h>
> +#include "clk-regmap-mux.h"
> +
> +static u8 rtk_clk_regmap_mux_get_parent(struct clk_hw *hw)
> +{
> +	struct rtk_clk_regmap_mux *clkm = to_rtk_clk_regmap_mux(hw);
> +	unsigned int num_parents = clk_hw_get_num_parents(hw);
> +	u32 val;
> +	int ret;
> +
> +	ret = regmap_read(clkm->clkr.regmap, clkm->mux_ofs, &val);
> +	if (ret)
> +		return 0xff;
> +
> +	val = (val >> clkm->shift) & clkm->mask;
> +
> +	return val >= num_parents ? 0xff : val;

This is not really useful, the core already rejects val >= num_parent.
So returning a higher number changes nothing as it stands

> +}
> +
> +static int rtk_clk_regmap_mux_set_parent(struct clk_hw *hw, u8 index)
> +{
> +	struct rtk_clk_regmap_mux *clkm = to_rtk_clk_regmap_mux(hw);
> +
> +	return regmap_update_bits(clkm->clkr.regmap, clkm->mux_ofs,
> +				  clkm->mask << clkm->shift, (u32)index << clkm->shift);
> +}
> +
> +const struct clk_ops rtk_clk_regmap_mux_ops = {
> +	.set_parent = rtk_clk_regmap_mux_set_parent,
> +	.get_parent = rtk_clk_regmap_mux_get_parent,
> +	.determine_rate = __clk_mux_determine_rate,
> +};
> +EXPORT_SYMBOL_NS_GPL(rtk_clk_regmap_mux_ops, "CLK_REALTEK");
> diff --git a/drivers/clk/realtek/clk-regmap-mux.h b/drivers/clk/realtek/clk-regmap-mux.h
> new file mode 100644
> index 000000000000..ad524bb86a19
> --- /dev/null
> +++ b/drivers/clk/realtek/clk-regmap-mux.h
> @@ -0,0 +1,43 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2017-2026 Realtek Semiconductor Corporation
> + * Author: Cheng-Yu Lee <cylee12@realtek.com>
> + */
> +
> +#ifndef __CLK_REALTEK_CLK_REGMAP_MUX_H
> +#define __CLK_REALTEK_CLK_REGMAP_MUX_H
> +
> +#include "clk-rtk-common.h"
> +
> +struct rtk_clk_regmap_mux {
> +	struct rtk_clk_regmap clkr;
> +	unsigned int mux_ofs;
> +	unsigned int mask;
> +	unsigned int shift;
> +};
> +
> +#define __rtk_clk_regmap_mux_hw(_p) __rtk_clk_regmap_hw(&(_p)->clkr)
> +
> +#define __RTK_CLK_REGMAP_MUX(_name, _parents, _ops, _flags, _ofs, _sft, _mask) \
> +	struct rtk_clk_regmap_mux _name = {                                    \
> +		.clkr.hw.init =                                                \
> +			CLK_HW_INIT_PARENTS(#_name, _parents, _ops, _flags),   \
> +		.mux_ofs = _ofs,                                               \
> +		.shift = _sft,                                                 \
> +		.mask = _mask,                                                 \
> +	}
> +
> +#define RTK_CLK_REGMAP_MUX(_name, _parents, _flags, _ofs, _sft, _mask)               \
> +	__RTK_CLK_REGMAP_MUX(_name, _parents, &rtk_clk_regmap_mux_ops, _flags, _ofs, \
> +			     _sft, _mask)
> +
> +static inline struct rtk_clk_regmap_mux *to_rtk_clk_regmap_mux(struct clk_hw *hw)
> +{
> +	struct rtk_clk_regmap *clkr = to_rtk_clk_regmap(hw);
> +
> +	return container_of(clkr, struct rtk_clk_regmap_mux, clkr);
> +}
> +
> +extern const struct clk_ops rtk_clk_regmap_mux_ops;
> +
> +#endif /* __CLK_REALTEK_CLK_REGMAP_MUX_H */
> -- 
> 2.43.0
> 
>