* [PATCH v2 1/6] dt-bindings: media: venus,common: relax clock/power-domain/iommu limits
2026-09-23 2:41 [PATCH v2 0/6] media: iris: add support for maili platform Wangao Wang
@ 2026-09-23 2:41 ` Wangao Wang
2026-09-23 12:12 ` Rob Herring (Arm)
2026-09-23 2:41 ` [PATCH v2 2/6] dt-bindings: media: qcom,maili-iris: Add Maili video codec Wangao Wang
` (4 subsequent siblings)
5 siblings, 1 reply; 8+ messages in thread
From: Wangao Wang @ 2026-09-23 2:41 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanimir Varbanov, Abhinav Kumar, Hans Verkuil,
Vishnu Reddy
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, Wangao Wang
Upcoming Soc's Iris4/5 video codec requires more clocks, power domain
entries and IOMMU mappings than the current limits allow. Relax the
common schema constraints to accommodate it.
Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com>
---
.../devicetree/bindings/media/qcom,venus-common.yaml | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/qcom,venus-common.yaml b/Documentation/devicetree/bindings/media/qcom,venus-common.yaml
index 68d5e592a028c5eecde04ce72cd5ae6815ba5c82..18891f0859eef7e8e3739a4b94e3abcdcb9d6009 100644
--- a/Documentation/devicetree/bindings/media/qcom,venus-common.yaml
+++ b/Documentation/devicetree/bindings/media/qcom,venus-common.yaml
@@ -20,11 +20,11 @@ properties:
clocks:
minItems: 3
- maxItems: 7
+ maxItems: 13
clock-names:
minItems: 3
- maxItems: 7
+ maxItems: 13
firmware-name:
maxItems: 1
@@ -41,11 +41,11 @@ properties:
power-domains:
minItems: 1
- maxItems: 4
+ maxItems: 9
power-domain-names:
minItems: 1
- maxItems: 4
+ maxItems: 9
'#address-cells':
const: 1
@@ -64,9 +64,10 @@ properties:
properties:
iommus:
- maxItems: 1
+ minItems: 1
+ maxItems: 3
iommu-ranges:
- maxItems: 1
+ maxItems: 2
required:
- iommus
- iommu-ranges
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 1/6] dt-bindings: media: venus,common: relax clock/power-domain/iommu limits
2026-09-23 2:41 ` [PATCH v2 1/6] dt-bindings: media: venus,common: relax clock/power-domain/iommu limits Wangao Wang
@ 2026-09-23 12:12 ` Rob Herring (Arm)
0 siblings, 0 replies; 8+ messages in thread
From: Rob Herring (Arm) @ 2026-09-23 12:12 UTC (permalink / raw)
To: Wangao Wang
Cc: linux-arm-msm, Stanimir Varbanov, Mauro Carvalho Chehab,
Vishnu Reddy, Abhinav Kumar, Vikash Garodia, linux-kernel,
linux-media, Hans Verkuil, Dikshita Agarwal, Bryan O'Donoghue,
Conor Dooley, Krzysztof Kozlowski, devicetree
On Wed, 23 Sep 2026 10:41:11 +0800, Wangao Wang wrote:
> Upcoming Soc's Iris4/5 video codec requires more clocks, power domain
> entries and IOMMU mappings than the current limits allow. Relax the
> common schema constraints to accommodate it.
>
> Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com>
> ---
> .../devicetree/bindings/media/qcom,venus-common.yaml | 13 +++++++------
> 1 file changed, 7 insertions(+), 6 deletions(-)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/media/qcom,sm8550-iris.example.dtb: video-codec@aa00000 (qcom,sm8550-iris): non-pixel:iommu-ranges: [[629145600, 3128950784]] is too short
from schema $id: http://devicetree.org/schemas/media/qcom,sm8550-iris.yaml
Documentation/devicetree/bindings/media/qcom,sm8550-iris.example.dtb: video-codec@aa00000 (qcom,sm8550-iris): Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'dma-ranges', 'non-pixel', 'pixel' were unexpected)
from schema $id: http://devicetree.org/schemas/media/qcom,sm8550-iris.yaml
Documentation/devicetree/bindings/media/qcom,sm8750-iris.example.dtb: video-codec@aa00000 (qcom,sm8750-iris): non-pixel:iommu-ranges: [[629145600, 3128950784]] is too short
from schema $id: http://devicetree.org/schemas/media/qcom,sm8750-iris.yaml
Documentation/devicetree/bindings/media/qcom,sm8750-iris.example.dtb: video-codec@aa00000 (qcom,sm8750-iris): Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'dma-ranges', 'interrupts', 'memory-region', 'non-pixel', 'pixel', 'reg' were unexpected)
from schema $id: http://devicetree.org/schemas/media/qcom,sm8750-iris.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260923-add_iris_for_maili-v2-1-7223738e330d@oss.qualcomm.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 2/6] dt-bindings: media: qcom,maili-iris: Add Maili video codec
2026-09-23 2:41 [PATCH v2 0/6] media: iris: add support for maili platform Wangao Wang
2026-09-23 2:41 ` [PATCH v2 1/6] dt-bindings: media: venus,common: relax clock/power-domain/iommu limits Wangao Wang
@ 2026-09-23 2:41 ` Wangao Wang
2026-09-23 2:41 ` [PATCH v2 3/6] media: iris: add AV1 decode buffer size support for vpu4x Wangao Wang
` (3 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Wangao Wang @ 2026-09-23 2:41 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanimir Varbanov, Abhinav Kumar, Hans Verkuil,
Vishnu Reddy
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, Wangao Wang
Add a devicetree binding for the Iris4 video encoder and decoder block
found on the Qualcomm Maili SoC.
Compared to the Iris3 generation, this block has
- separate clocks for BSE (Bitstream Engine) and VPP (Video Processing
Pipeline).
- power domain for VPP (Video Processing Pipeline).
- different reset lines.
Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com>
---
.../devicetree/bindings/media/qcom,maili-iris.yaml | 229 +++++++++++++++++++++
1 file changed, 229 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/qcom,maili-iris.yaml b/Documentation/devicetree/bindings/media/qcom,maili-iris.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..4ddc4df8481b52661b314821a9fac68870d8ca6c
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,maili-iris.yaml
@@ -0,0 +1,229 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,maili-iris.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Maili SoC Iris video encoder and decoder
+
+maintainers:
+ - Vikash Garodia <vikash.garodia@oss.qualcomm.com>
+ - Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
+
+description:
+ The Iris video processing unit on Qualcomm Maili SoC is a video encode and
+ decode accelerator.
+
+properties:
+ compatible:
+ enum:
+ - qcom,maili-iris
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 8
+
+ clock-names:
+ items:
+ - const: iface
+ - const: core
+ - const: vcodec0_core
+ - const: iface1
+ - const: core_freerun
+ - const: vcodec0_core_freerun
+ - const: vcodec_bse
+ - const: vcodec_vpp0
+
+ firmware-name:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: cpu-cfg
+ - const: video-mem
+
+ power-domains:
+ maxItems: 5
+
+ power-domain-names:
+ items:
+ - const: venus
+ - const: vcodec0
+ - const: mxc
+ - const: mmcx
+ - const: vpp0
+
+ resets:
+ maxItems: 4
+
+ reset-names:
+ items:
+ - const: bus0
+ - const: bus1
+ - const: core
+ - const: vcodec0_core
+
+ iommus:
+ maxItems: 4
+
+ dma-coherent: true
+
+ operating-points-v2: true
+
+ opp-table:
+ type: object
+
+required:
+ - compatible
+ - dma-coherent
+ - interconnects
+ - interconnect-names
+ - power-domain-names
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: qcom,venus-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,hawi-gcc.h>
+ #include <dt-bindings/clock/qcom,maili-videocc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interconnect/qcom,maili-rpmh.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ video-codec@2000000 {
+ compatible = "qcom,maili-iris";
+ reg = <0x02000000 0xf0000>;
+
+ interrupts = <GIC_ESPI 238 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+ <&videocc VIDEO_CC_MVS0C_CLK>,
+ <&videocc VIDEO_CC_MVS0_CLK>,
+ <&gcc GCC_VIDEO_AXI0C_CLK>,
+ <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>,
+ <&videocc VIDEO_CC_MVS0_FREERUN_CLK>,
+ <&videocc VIDEO_CC_MVS0B_CLK>,
+ <&videocc VIDEO_CC_MVS0_VPP0_CLK>;
+ clock-names = "iface",
+ "core",
+ "vcodec0_core",
+ "iface1",
+ "core_freerun",
+ "vcodec0_core_freerun",
+ "vcodec_bse",
+ "vcodec_vpp0";
+
+ dma-coherent;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_IRIS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "cpu-cfg",
+ "video-mem";
+
+ memory-region = <&video_mem>;
+
+ power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
+ <&videocc VIDEO_CC_MVS0_GDSC>,
+ <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&videocc VIDEO_CC_MVS0_VPP0_GDSC>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "mxc",
+ "mmcx",
+ "vpp0";
+
+ resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
+ <&gcc GCC_VIDEO_AXI0C_CLK_ARES>,
+ <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>,
+ <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>;
+ reset-names = "bus0",
+ "bus1",
+ "core",
+ "vcodec0_core";
+
+ operating-points-v2 = <&iris_opp_table>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-ranges = <0x0 0x0 0xffc00000>;
+
+ non-pixel {
+ iommus = <&apps_smmu 0x1540 0x0000>,
+ <&apps_smmu 0x1620 0x0000>,
+ <&apps_smmu 0x1544 0x0000>;
+ iommu-ranges = <0x25800000 0xda400000>;
+ };
+
+ pixel {
+ iommus = <&apps_smmu 0x1543 0x0000>;
+ };
+
+ iris_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-240000000 {
+ opp-hz = /bits/ 64 <240000000 240000000 360000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d2>,
+ <&rpmhpd_opp_low_svs_d1>;
+ };
+
+ opp-338000000 {
+ opp-hz = /bits/ 64 <338000000 338000000 507000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-420000000 {
+ opp-hz = /bits/ 64 <420000000 420000000 630000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs>;
+ };
+
+ opp-444000000 {
+ opp-hz = /bits/ 64 <444000000 444000000 666000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000 533000000 800000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_nom>;
+ };
+
+ opp-630000000 {
+ opp-hz = /bits/ 64 <630000000 630000000 1104000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_turbo>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000 630000000 1260000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_turbo_l1>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000 800000000 1260000000>;
+ required-opps = <&rpmhpd_opp_nom>,
+ <&rpmhpd_opp_turbo_l3>;
+ };
+ };
+ };
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 3/6] media: iris: add AV1 decode buffer size support for vpu4x
2026-09-23 2:41 [PATCH v2 0/6] media: iris: add support for maili platform Wangao Wang
2026-09-23 2:41 ` [PATCH v2 1/6] dt-bindings: media: venus,common: relax clock/power-domain/iommu limits Wangao Wang
2026-09-23 2:41 ` [PATCH v2 2/6] dt-bindings: media: qcom,maili-iris: Add Maili video codec Wangao Wang
@ 2026-09-23 2:41 ` Wangao Wang
2026-09-23 2:41 ` [PATCH v2 4/6] media: iris: add maili platform data Wangao Wang
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Wangao Wang @ 2026-09-23 2:41 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanimir Varbanov, Abhinav Kumar, Hans Verkuil,
Vishnu Reddy
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, Wangao Wang
Add necessary buffer size calculation to support AV1 decode for vpu4x
- wire AV1 into iris_vpu4x_dec_line_size() via hfi_buffer_line_av1d()
- add hfi_vpu4x_buffer_persist_av1d() for the vpu4x's persist buffer
size calculation
- add BUF_PARTIAL to the vpu4x decoder dispatch table, which AV1D
requires
Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 34 ++++++++++++++++++++--
drivers/media/platform/qcom/iris/iris_vpu_buffer.h | 1 +
2 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
index faebb54728660cc621f8822dabf2e44ce8c55c58..bb8135bd238b670fb5806120493b2603d9c2b0fb 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
@@ -1833,6 +1833,8 @@ static u32 iris_vpu4x_dec_line_size(struct iris_inst *inst)
else if (inst->codec == V4L2_PIX_FMT_VP9)
return hfi_vpu4x_buffer_line_vp9d(width, height, out_min_count, is_opb,
num_vpp_pipes);
+ else if (inst->codec == V4L2_PIX_FMT_AV1)
+ return hfi_buffer_line_av1d(width, height, is_opb, num_vpp_pipes);
return 0;
}
@@ -1856,14 +1858,39 @@ static u32 hfi_vpu4x_buffer_persist_vp9d(void)
HDR10_HIST_EXTRADATA_SIZE;
}
+static u32 hfi_vpu4x_buffer_persist_av1d(u32 max_width, u32 max_height,
+ u32 total_ref_count, u32 rpu_enabled)
+{
+ u32 comv_size = hfi_buffer_comv_av1d(max_width, max_height, total_ref_count);
+ u32 seq_hdr = SIZE_AV1D_SEQUENCE_HEADER * 2 + SIZE_AV1D_METADATA;
+ u32 per_pic = AV1D_NUM_HW_PIC_BUF *
+ (SIZE_AV1D_TILE_OFFSET + SIZE_AV1D_QM + SIZE_AV1D_ARP + SIZE_AV1D_METADATA);
+ u32 frame_hdr = AV1D_NUM_FRAME_HEADERS *
+ (SIZE_AV1D_FRAME_HEADER + 2 * SIZE_AV1D_PROB_TABLE);
+ u32 extradata = HDR10_HIST_EXTRADATA_SIZE +
+ rpu_enabled * NUM_HW_PIC_BUF * SIZE_DOLBY_RPU_METADATA;
+
+ return ALIGN(seq_hdr + per_pic + frame_hdr + comv_size + extradata, DMA_ALIGNMENT);
+}
+
static u32 iris_vpu4x_dec_persist_size(struct iris_inst *inst)
{
- if (inst->codec == V4L2_PIX_FMT_H264)
+ struct platform_inst_caps *caps;
+
+ if (inst->codec == V4L2_PIX_FMT_H264) {
return hfi_buffer_persist_h264d();
- else if (inst->codec == V4L2_PIX_FMT_HEVC)
+ } else if (inst->codec == V4L2_PIX_FMT_HEVC) {
return hfi_vpu4x_buffer_persist_h265d(0);
- else if (inst->codec == V4L2_PIX_FMT_VP9)
+ } else if (inst->codec == V4L2_PIX_FMT_VP9) {
return hfi_vpu4x_buffer_persist_vp9d();
+ } else if (inst->codec == V4L2_PIX_FMT_AV1) {
+ caps = inst->core->iris_platform_data->inst_caps;
+ if (inst->fw_caps[DRAP].value)
+ return hfi_vpu4x_buffer_persist_av1d(caps->max_frame_width,
+ caps->max_frame_height, 16, 0);
+ else
+ return hfi_vpu4x_buffer_persist_av1d(0, 0, 0, 0);
+ }
return 0;
}
@@ -2163,6 +2190,7 @@ u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_typ
{BUF_PERSIST, iris_vpu4x_dec_persist_size },
{BUF_DPB, iris_vpu_dec_dpb_size },
{BUF_SCRATCH_1, iris_vpu_dec_scratch1_size },
+ {BUF_PARTIAL, iris_vpu_dec_partial_size },
};
static const struct iris_vpu_buf_type_handle enc_internal_buf_type_handle[] = {
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
index 8c0d6b7b5de85f7d7aaa8fc36218e8d095419569..c7020931a642f0484b6f84af7ab51242e1845458 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
@@ -116,6 +116,7 @@ struct iris_inst;
#define SIZE_AV1D_TILE_OFFSET 65536
#define SIZE_AV1D_QM 3328
#define SIZE_AV1D_PROB_TABLE 22784
+#define SIZE_AV1D_ARP 9728
#define SIZE_SLICE_CMD_BUFFER (ALIGN(20480, 256))
#define SIZE_SPS_PPS_SLICE_HDR (2048 + 4096)
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 4/6] media: iris: add maili platform data
2026-09-23 2:41 [PATCH v2 0/6] media: iris: add support for maili platform Wangao Wang
` (2 preceding siblings ...)
2026-09-23 2:41 ` [PATCH v2 3/6] media: iris: add AV1 decode buffer size support for vpu4x Wangao Wang
@ 2026-09-23 2:41 ` Wangao Wang
2026-09-23 2:41 ` [PATCH v2 5/6] arm64: dts: qcom: maili: add iris video codec node Wangao Wang
2026-09-23 2:41 ` [PATCH v2 6/6] arm64: dts: qcom: maili: enable iris on mtp board Wangao Wang
5 siblings, 0 replies; 8+ messages in thread
From: Wangao Wang @ 2026-09-23 2:41 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanimir Varbanov, Abhinav Kumar, Hans Verkuil,
Vishnu Reddy
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, Wangao Wang
Add platform data for the Maili Iris VPU4 block so the driver can
match the qcom,maili-iris compatible and initialize the hardware.
Describe the Maili-specific clocks, power domains, firmware, resets,
bandwidth data, DMA range, secure memory configuration, and decode
capabilities.
Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/Makefile | 1 +
.../platform/qcom/iris/iris_platform_common.h | 4 +
.../media/platform/qcom/iris/iris_platform_maili.h | 40 ++++++++++
.../media/platform/qcom/iris/iris_platform_vpu4x.c | 86 ++++++++++++++++++++++
drivers/media/platform/qcom/iris/iris_probe.c | 4 +
5 files changed, 135 insertions(+)
diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile
index 48e415cbc4390bc596f6239fefa2a2ad2cd3a2bb..f8a017d878d620fe1d82708624595583aa2ffd99 100644
--- a/drivers/media/platform/qcom/iris/Makefile
+++ b/drivers/media/platform/qcom/iris/Makefile
@@ -14,6 +14,7 @@ qcom-iris-objs += iris_buffer.o \
iris_hfi_queue.o \
iris_platform_vpu2.o \
iris_platform_vpu3x.o \
+ iris_platform_vpu4x.o \
iris_power.o \
iris_probe.o \
iris_resources.o \
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 9748095091461ba13443c63955a42906fa4f050c..61639d72bdcc9917983096e5b8f5905936784623 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -39,6 +39,9 @@ struct iris_inst;
#define MAX_HEVC_VBR_LAYER_HP_SLIDING_WINDOW 5
#define MAX_HIER_CODING_LAYER_GEN1 6
+#define VIDEO_REGION_VM0_SECURE_NP_ID 1
+#define VIDEO_REGION_VM0_NONSECURE_NP_ID 5
+
enum stage_type {
STAGE_1 = 1,
STAGE_2 = 2,
@@ -54,6 +57,7 @@ extern const struct iris_firmware_data iris_hfi_gen1_data;
extern const struct iris_firmware_data iris_hfi_gen2_data;
extern const struct iris_firmware_data iris_hfi_milos_data;
+extern const struct iris_platform_data maili_data;
extern const struct iris_platform_data milos_data;
extern const struct iris_platform_data qcs8300_data;
extern const struct iris_platform_data sc7280_data;
diff --git a/drivers/media/platform/qcom/iris/iris_platform_maili.h b/drivers/media/platform/qcom/iris/iris_platform_maili.h
new file mode 100644
index 0000000000000000000000000000000000000000..b0c48743485a176fb9855a841955413d7093c7d4
--- /dev/null
+++ b/drivers/media/platform/qcom/iris/iris_platform_maili.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __IRIS_PLATFORM_MAILI_H__
+#define __IRIS_PLATFORM_MAILI_H__
+
+static const char *const maili_pmdomain_table[] = {
+ "venus",
+ "vcodec0",
+ "vpp0",
+};
+
+static const struct platform_clk_data maili_clk_table[] = {
+ { IRIS_AXI_CLK, "iface" },
+ { IRIS_AXI1_CLK, "iface1" },
+ { IRIS_CTRL_CLK, "core" },
+ { IRIS_CTRL_FREERUN_CLK, "core_freerun" },
+ { IRIS_HW_CLK, "vcodec0_core" },
+ { IRIS_HW_FREERUN_CLK, "vcodec0_core_freerun" },
+ { IRIS_BSE_HW_CLK, "vcodec_bse" },
+ { IRIS_VPP0_HW_CLK, "vcodec_vpp0" },
+};
+
+static const char *const maili_opp_clk_table[] = {
+ "vcodec0_core",
+ "vcodec_bse",
+ "core",
+ NULL,
+};
+
+static const char *const vpu4x_clk_reset_table[] = {
+ "bus0",
+ "bus1",
+ "core",
+ "vcodec0_core",
+};
+
+#endif
diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c
new file mode 100644
index 0000000000000000000000000000000000000000..d39acb1552dca4ae61dbc7875040be25c196aba6
--- /dev/null
+++ b/drivers/media/platform/qcom/iris/iris_platform_vpu4x.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include "iris_core.h"
+#include "iris_ctrls.h"
+#include "iris_hfi_gen2.h"
+#include "iris_hfi_gen2_defines.h"
+#include "iris_platform_common.h"
+#include "iris_vpu_buffer.h"
+#include "iris_vpu_common.h"
+
+#include "iris_platform_sm8550.h"
+#include "iris_platform_maili.h"
+
+static const struct iris_firmware_desc iris_vpu40_p1_s8_gen2_desc = {
+ .firmware_data = &iris_hfi_gen2_data,
+ .get_vpu_buffer_size = iris_vpu4x_buf_size,
+ .fwname = "qcom/vpu/vpu40_p1_s8.mbn",
+};
+
+static const u32 iris_fmts_vpu4x_dec[] = {
+ [IRIS_FMT_H264] = V4L2_PIX_FMT_H264,
+ [IRIS_FMT_HEVC] = V4L2_PIX_FMT_HEVC,
+ [IRIS_FMT_VP9] = V4L2_PIX_FMT_VP9,
+ [IRIS_FMT_AV1] = V4L2_PIX_FMT_AV1,
+};
+
+static const struct icc_info iris_icc_info_vpu4x[] = {
+ { "cpu-cfg", 1000, 1000 },
+ { "video-mem", 1000, 15000000 },
+};
+
+static const struct bw_info iris_bw_table_dec_vpu4x[] = {
+ { ((4096 * 2160) / 256) * 60, 1608000 },
+ { ((4096 * 2160) / 256) * 30, 826000 },
+ { ((1920 * 1080) / 256) * 60, 567000 },
+ { ((1920 * 1080) / 256) * 30, 294000 },
+};
+
+static const char * const iris_opp_pd_table_vpu4x[] = { "mxc", "mmcx" };
+
+static const struct tz_cp_config tz_cp_config_vpu4x[] = {
+ {
+ .cp_start = VIDEO_REGION_VM0_SECURE_NP_ID,
+ .cp_size = 0,
+ .cp_nonpixel_start = 0x01000000,
+ .cp_nonpixel_size = 0x24800000,
+ },
+ {
+ .cp_start = VIDEO_REGION_VM0_NONSECURE_NP_ID,
+ .cp_size = 0,
+ .cp_nonpixel_start = 0x25800000,
+ .cp_nonpixel_size = 0xda400000,
+ },
+};
+
+const struct iris_platform_data maili_data = {
+ .firmware_desc_gen2 = &iris_vpu40_p1_s8_gen2_desc,
+ .vpu_ops = &iris_vpu4x_ops,
+ .icc_tbl = iris_icc_info_vpu4x,
+ .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu4x),
+ .clk_rst_tbl = vpu4x_clk_reset_table,
+ .clk_rst_tbl_size = ARRAY_SIZE(vpu4x_clk_reset_table),
+ .bw_tbl_dec = iris_bw_table_dec_vpu4x,
+ .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu4x),
+ .pmdomain_tbl = maili_pmdomain_table,
+ .pmdomain_tbl_size = ARRAY_SIZE(maili_pmdomain_table),
+ .opp_pd_tbl = iris_opp_pd_table_vpu4x,
+ .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu4x),
+ .clk_tbl = maili_clk_table,
+ .clk_tbl_size = ARRAY_SIZE(maili_clk_table),
+ .opp_clk_tbl = maili_opp_clk_table,
+ /* Upper bound of DMA address range */
+ .dma_mask = 0xffc00000 - 1,
+ .inst_iris_fmts = iris_fmts_vpu4x_dec,
+ .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu4x_dec),
+ .inst_caps = &platform_inst_cap_sm8550,
+ .tz_cp_config_data = tz_cp_config_vpu4x,
+ .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu4x),
+ .num_vpp_pipe = 1,
+ .max_session_count = 16,
+ .max_core_mbpf = NUM_MBS_8K,
+ .max_core_mbps = NUM_MBS_8K * 30,
+};
diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
index 4bdb078d83b5c331869dab2409bc4d10ab302737..be8a102e239c34620d540c54f1f034a9236da7a7 100644
--- a/drivers/media/platform/qcom/iris/iris_probe.c
+++ b/drivers/media/platform/qcom/iris/iris_probe.c
@@ -427,6 +427,10 @@ static const struct dev_pm_ops iris_pm_ops = {
};
static const struct of_device_id iris_dt_match[] = {
+ {
+ .compatible = "qcom,maili-iris",
+ .data = &maili_data,
+ },
{
.compatible = "qcom,milos-iris",
.data = &milos_data,
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 5/6] arm64: dts: qcom: maili: add iris video codec node
2026-09-23 2:41 [PATCH v2 0/6] media: iris: add support for maili platform Wangao Wang
` (3 preceding siblings ...)
2026-09-23 2:41 ` [PATCH v2 4/6] media: iris: add maili platform data Wangao Wang
@ 2026-09-23 2:41 ` Wangao Wang
2026-09-23 2:41 ` [PATCH v2 6/6] arm64: dts: qcom: maili: enable iris on mtp board Wangao Wang
5 siblings, 0 replies; 8+ messages in thread
From: Wangao Wang @ 2026-09-23 2:41 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanimir Varbanov, Abhinav Kumar, Hans Verkuil,
Vishnu Reddy
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, Wangao Wang
Add the iris video codec device node for the maili SoC, describing the
register space, interrupt, five power domains, eight clocks, two
interconnect paths for CPU config and video memory bandwidth, IOMMU
Mappings, and the operating point table covering 240 MHz to 1000 MHz.
Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/maili.dtsi | 126 ++++++++++++++++++++++++++++++++++++
1 file changed, 126 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/maili.dtsi b/arch/arm64/boot/dts/qcom/maili.dtsi
index 886d307e536be6152906e344289d5b3fb290f0a4..3d9792915112554842256534ba4b85adf3a1441a 100644
--- a/arch/arm64/boot/dts/qcom/maili.dtsi
+++ b/arch/arm64/boot/dts/qcom/maili.dtsi
@@ -3591,6 +3591,132 @@ ice: crypto@1d88000 {
power-domains = <&gcc GCC_UFS_PHY_GDSC>;
};
+ iris: video-codec@2000000 {
+ compatible = "qcom,maili-iris";
+ reg = <0x0 0x02000000 0x0 0xf0000>;
+
+ interrupts = <GIC_ESPI 238 IRQ_TYPE_LEVEL_HIGH>;
+
+ power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
+ <&videocc VIDEO_CC_MVS0_GDSC>,
+ <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&videocc VIDEO_CC_MVS0_VPP0_GDSC>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "mxc",
+ "mmcx",
+ "vpp0";
+
+ clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+ <&videocc VIDEO_CC_MVS0C_CLK>,
+ <&videocc VIDEO_CC_MVS0_CLK>,
+ <&gcc GCC_VIDEO_AXI0C_CLK>,
+ <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>,
+ <&videocc VIDEO_CC_MVS0_FREERUN_CLK>,
+ <&videocc VIDEO_CC_MVS0B_CLK>,
+ <&videocc VIDEO_CC_MVS0_VPP0_CLK>;
+ clock-names = "iface",
+ "core",
+ "vcodec0_core",
+ "iface1",
+ "core_freerun",
+ "vcodec0_core_freerun",
+ "vcodec_bse",
+ "vcodec_vpp0";
+
+ operating-points-v2 = <&iris_opp_table>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_IRIS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "cpu-cfg",
+ "video-mem";
+
+ memory-region = <&video_mem>;
+
+ resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
+ <&gcc GCC_VIDEO_AXI0C_CLK_ARES>,
+ <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>,
+ <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>;
+ reset-names = "bus0",
+ "bus1",
+ "core",
+ "vcodec0_core";
+
+ dma-coherent;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-ranges = <0x0 0x0 0x0 0xffc00000>;
+
+ status = "disabled";
+
+ iris_non_pixel: non-pixel {
+ iommus = <&apps_smmu 0x1540 0x0000>,
+ <&apps_smmu 0x1620 0x0000>,
+ <&apps_smmu 0x1544 0x0000>;
+ iommu-ranges = <0x25800000 0xda400000>;
+ };
+
+ iris_pixel: pixel {
+ iommus = <&apps_smmu 0x1543 0x0000>;
+ };
+
+ iris_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-240000000 {
+ opp-hz = /bits/ 64 <240000000 240000000 360000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d2>,
+ <&rpmhpd_opp_low_svs_d1>;
+ };
+
+ opp-338000000 {
+ opp-hz = /bits/ 64 <338000000 338000000 507000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-420000000 {
+ opp-hz = /bits/ 64 <420000000 420000000 630000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs>;
+ };
+
+ opp-444000000 {
+ opp-hz = /bits/ 64 <444000000 444000000 666000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000 533000000 800000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_nom>;
+ };
+
+ opp-630000000 {
+ opp-hz = /bits/ 64 <630000000 630000000 1104000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_turbo>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000 630000000 1260000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_turbo_l1>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000 800000000 1260000000>;
+ required-opps = <&rpmhpd_opp_nom>,
+ <&rpmhpd_opp_turbo_l3>;
+ };
+ };
+ };
+
videocc: clock-controller@20f0000 {
compatible = "qcom,maili-videocc";
reg = <0x0 0x020f0000 0x0 0x10000>;
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 6/6] arm64: dts: qcom: maili: enable iris on mtp board
2026-09-23 2:41 [PATCH v2 0/6] media: iris: add support for maili platform Wangao Wang
` (4 preceding siblings ...)
2026-09-23 2:41 ` [PATCH v2 5/6] arm64: dts: qcom: maili: add iris video codec node Wangao Wang
@ 2026-09-23 2:41 ` Wangao Wang
5 siblings, 0 replies; 8+ messages in thread
From: Wangao Wang @ 2026-09-23 2:41 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stanimir Varbanov, Abhinav Kumar, Hans Verkuil,
Vishnu Reddy
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, Wangao Wang
Enable the iris video codec on the maili MTP reference board.
Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/maili-mtp.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/maili-mtp.dts b/arch/arm64/boot/dts/qcom/maili-mtp.dts
index 1fdc91e03271c40640910b57f3187311b6077ea9..88b452ec7e985dc1f1b87a56a16aa2e5dddf96b4 100644
--- a/arch/arm64/boot/dts/qcom/maili-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/maili-mtp.dts
@@ -743,6 +743,10 @@ vreg_l7n_3p3: ldo7 {
};
};
+&iris {
+ status = "okay";
+};
+
&pcie0 {
status = "okay";
};
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread