[PATCH v3 0/5] arm64: dts: renesas: Enable ISP and IVC on RZ/V2H EVK

[PATCH v3 0/5] arm64: dts: renesas: Enable ISP and IVC on RZ/V2H EVK

[Linus Walleij]

Describe the optional ISP DMA line-tick and IVC frame-start/frame-stop
interrupts. Add the RZ/V2H(P) IVC and Arm Mali-C55 ISP nodes, connect their
video endpoints, and enable both blocks on the RZ/V2H EVK.

After these patches, and enabling the right Linux drivers, we get
this in the console:
mali-c55 16080000.isp: Detected Mali-C55 ISP 9000043.31032022.0

This was done in order to enable booting mainline with mainline
device trees.

Assisted-by: LLM
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
Changes in v3:
- Correct the ISP video and register clock/reset mappings by swapping
  vclk/hclk and vresetn/hresetn.
- Add an optional ISP power-domain binding and attach the RZ/V2H ISP
  to the CPG power domain.
- Link to v2: https://patch.msgid.link/20260925-mali-c55-renesas-dts-v2-0-69f728a474a2@kernel.org

Changes in v2:
- Add separate IVC and ISP binding patches describing the optional IVC
  frame-start/frame-stop completion and ISP DMA line-tick IRQs.
  Show all six IRQs in the examples using consecutive mock numbers.
- Add the IVC frame-start/stop and ISP DMA line-tick interrupt lines
  using the confirmed SPI assignments, addressing Geert's IRQ review.
- Correct the IVC and ISP register sizes to 64 KiB and 512 KiB,
  respectively, as requested by Geert. GPV_VIDEO0 is a separate bus
  interconnect region.
- Compact the clock and reset properties and remove blank lines between
  properties, following Geert's review.
- Link to v1: https://patch.msgid.link/20260922-mali-c55-renesas-dts-v1-0-cd63cdb51033@kernel.org

---
Daniel Scally (2):
      arm64: dts: renesas: r9a09g057: Add IVC and ISP nodes
      arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add ISP and IVC nodes

Linus Walleij (3):
      dt-bindings: media: renesas,r9a09g057-ivc: Describe additional interrupts
      dt-bindings: media: arm,mali-c55: Describe DMA line-tick interrupts
      dt-bindings: media: arm,mali-c55: Add power domain

 .../devicetree/bindings/media/arm,mali-c55.yaml    | 15 ++++++--
 .../bindings/media/renesas,r9a09g057-ivc.yaml      | 11 ++++--
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi         | 42 ++++++++++++++++++++++
 .../boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts    |  8 +++++
 4 files changed, 72 insertions(+), 4 deletions(-)
---
base-commit: cee9395acd8043be0644b25c34bfa86623f2b935
change-id: 20260922-mali-c55-renesas-dts-74d4727f59e5

Best regards,
--  
Linus Walleij <linusw@kernel.org>

[PATCH v3 1/5] dt-bindings: media: renesas,r9a09g057-ivc: Describe additional interrupts

[Linus Walleij]

The RZ/V2H IVC provides input frame-start and frame-stop completion
interrupts alongside its input frame-end interrupt.

Describe these optional interrupts, keeping frame end first and requiring
only that entry to preserve support for existing device trees. Extend the
example to show all three interrupts using mock interrupt numbers.

Assisted-by: LLM
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
 .../devicetree/bindings/media/renesas,r9a09g057-ivc.yaml      | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml b/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml
index c09cbd8c9e35..3eeb1a92c9cf 100644
--- a/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml
+++ b/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml
@@ -21,7 +21,11 @@ properties:
     maxItems: 1
 
   interrupts:
-    maxItems: 1
+    minItems: 1
+    items:
+      - description: Image input frame-end interrupt
+      - description: Image input frame-start interrupt
+      - description: Frame-stop processing completion interrupt
 
   clocks:
     items:
@@ -92,7 +96,10 @@ examples:
                <&cpg 0xd3>;
       reset-names = "reg", "axi", "isp";
 
-      interrupts = <GIC_SPI 861 IRQ_TYPE_EDGE_RISING>;
+      /* Example interrupt numbers. */
+      interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 
       port {
         ivc_out: endpoint {

-- 
2.55.0

[PATCH v3 2/5] dt-bindings: media: arm,mali-c55: Describe DMA line-tick interrupts

[Linus Walleij]

Mali-C55 exposes separate full-resolution and UV DMA writer line-tick
interrupts in addition to its combined core interrupt.

Describe these optional interrupts, keeping the core interrupt first and
requiring only that entry to preserve support for existing device trees.
Extend the example to show all three interrupts using mock interrupt
numbers.

Assisted-by: LLM
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
 Documentation/devicetree/bindings/media/arm,mali-c55.yaml | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/arm,mali-c55.yaml b/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
index fc4fcd19922a..8fcc46660b75 100644
--- a/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
+++ b/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
@@ -18,7 +18,11 @@ properties:
     maxItems: 1
 
   interrupts:
-    maxItems: 1
+    minItems: 1
+    items:
+      - description: Combined ISP core interrupt
+      - description: Full-resolution DMA writer line-tick interrupt
+      - description: Full-resolution UV DMA writer line-tick interrupt
 
   clocks:
     items:
@@ -75,7 +79,10 @@ examples:
       clock-names = "vclk", "aclk", "hclk";
       resets = <&resets 0>, <&resets 1>, <&resets 2>;
       reset-names = "vresetn", "aresetn", "hresetn";
-      interrupts = <GIC_SPI 861 IRQ_TYPE_EDGE_RISING>;
+      /* Example interrupt numbers. */
+      interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+                   <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
 
       port {
         isp_in: endpoint {

-- 
2.55.0

[PATCH v3 3/5] dt-bindings: media: arm,mali-c55: Add power domain

[Linus Walleij]

Some Mali-C55 integrations place the ISP in a power domain. In
particular, RZ/V2H uses the CPG domain to manage its module clocks
through runtime PM.

Allow a single power domain and describe it in the example. Keep the
property optional for integrations that do not expose a power domain.

Assisted-by: LLM
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
 Documentation/devicetree/bindings/media/arm,mali-c55.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/media/arm,mali-c55.yaml b/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
index 8fcc46660b75..3a11d3f8488a 100644
--- a/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
+++ b/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
@@ -36,6 +36,9 @@ properties:
       - const: aclk
       - const: hclk
 
+  power-domains:
+    maxItems: 1
+
   resets:
     items:
       - description: vclk domain reset
@@ -77,6 +80,7 @@ examples:
       reg = <0x400000 0x200000>;
       clocks = <&clk 0>, <&clk 1>, <&clk 2>;
       clock-names = "vclk", "aclk", "hclk";
+      power-domains = <&power>;
       resets = <&resets 0>, <&resets 1>, <&resets 2>;
       reset-names = "vresetn", "aresetn", "hresetn";
       /* Example interrupt numbers. */

-- 
2.55.0

[PATCH v3 4/5] arm64: dts: renesas: r9a09g057: Add IVC and ISP nodes

[Linus Walleij]

From: Daniel Scally <dan.scally@ideasonboard.com>

Add the Input Video Control Block and Arm Mali-C55 ISP to the device
tree file for the RZ/V2H(P) SoC.

[Rebase onto v7.3-rc1, place the nodes in address order, add the
 missing interrupt and sort them. - Linus Walleij]

Assisted-by: LLM
Signed-off-by: Daniel Scally <dan.scally@ideasonboard.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 42 ++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 639693d464a7..219ba058c9f5 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -1839,6 +1839,48 @@ queue3 {
 			};
 		};
 
+		ivc: isp-input@16040000 {
+			compatible = "renesas,r9a09g057-ivc";
+			reg = <0 0x16040000 0 0x10000>;
+			clocks = <&cpg CPG_MOD 0xe3>, <&cpg CPG_MOD 0xe4>,
+				 <&cpg CPG_MOD 0xe5>;
+			clock-names = "reg", "axi", "isp";
+			interrupts = <GIC_SPI 861 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 860 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&cpg>;
+			resets = <&cpg 0xd4>, <&cpg 0xd1>, <&cpg 0xd3>;
+			reset-names = "reg", "axi", "isp";
+			status = "disabled";
+
+			port {
+				ivc_out: endpoint {
+					remote-endpoint = <&isp_in>;
+				};
+			};
+		};
+
+		isp: isp@16080000 {
+			compatible = "arm,mali-c55";
+			reg = <0 0x16080000 0 0x80000>;
+			clocks = <&cpg CPG_MOD 0xe5>, <&cpg CPG_MOD 0xe4>,
+				 <&cpg CPG_MOD 0xe2>;
+			clock-names = "vclk", "aclk", "hclk";
+			interrupts = <GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 865 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 866 IRQ_TYPE_EDGE_RISING>;
+			power-domains = <&cpg>;
+			resets = <&cpg 0xd3>, <&cpg 0xd1>, <&cpg 0xd2>;
+			reset-names = "vresetn", "aresetn", "hresetn";
+			status = "disabled";
+
+			port {
+				isp_in: endpoint {
+					remote-endpoint = <&ivc_out>;
+				};
+			};
+		};
+
 		dsi: dsi@16430000 {
 			compatible = "renesas,r9a09g057-mipi-dsi";
 			reg = <0 0x16430000 0 0x20000>;

-- 
2.55.0

[PATCH v3 5/5] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add ISP and IVC nodes

[Linus Walleij]

From: Daniel Scally <dan.scally@ideasonboard.com>

Add nodes to devicetree enabling the ISP and IVC that are found on
the RZ/V2H(P) SoC.

[Rebase onto v7.3-rc1 and sort the board overrides by label.
 - Linus Walleij]

Assisted-by: LLM
Signed-off-by: Daniel Scally <dan.scally@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
 arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
index 637fc92dcc26..74b75be599ae 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
@@ -305,6 +305,14 @@ versa3: clock-generator@69 {
 	};
 };
 
+&isp {
+	status = "okay";
+};
+
+&ivc {
+	status = "okay";
+};
+
 &mdio0 {
 	phy0: ethernet-phy@0 {
 		compatible = "ethernet-phy-id0022.1640";

-- 
2.55.0

Re: [PATCH v3 2/5] dt-bindings: media: arm,mali-c55: Describe DMA line-tick interrupts

[Rob Herring (Arm)]

On Mon, 28 Sep 2026 14:21:48 +0200, Linus Walleij wrote:
> Mali-C55 exposes separate full-resolution and UV DMA writer line-tick
> interrupts in addition to its combined core interrupt.
> 
> Describe these optional interrupts, keeping the core interrupt first and
> requiring only that entry to preserve support for existing device trees.
> Extend the example to show all three interrupts using mock interrupt
> numbers.
> 
> Assisted-by: LLM
> Signed-off-by: Linus Walleij <linusw@kernel.org>
> ---
>  Documentation/devicetree/bindings/media/arm,mali-c55.yaml | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH v3 3/5] dt-bindings: media: arm,mali-c55: Add power domain

[Rob Herring (Arm)]

On Mon, 28 Sep 2026 14:21:49 +0200, Linus Walleij wrote:
> Some Mali-C55 integrations place the ISP in a power domain. In
> particular, RZ/V2H uses the CPG domain to manage its module clocks
> through runtime PM.
> 
> Allow a single power domain and describe it in the example. Keep the
> property optional for integrations that do not expose a power domain.
> 
> Assisted-by: LLM
> Signed-off-by: Linus Walleij <linusw@kernel.org>
> ---
>  Documentation/devicetree/bindings/media/arm,mali-c55.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH v3 0/5] arm64: dts: renesas: Enable ISP and IVC on RZ/V2H EVK

[Linus Walleij]

Hi Geert/Magnus,

On Mon, Sep 28, 2026 at 2:21 PM Linus Walleij <linusw@kernel.org> wrote:

> Describe the optional ISP DMA line-tick and IVC frame-start/frame-stop
> interrupts. Add the RZ/V2H(P) IVC and Arm Mali-C55 ISP nodes, connect their
> video endpoints, and enable both blocks on the RZ/V2H EVK.
>
> After these patches, and enabling the right Linux drivers, we get
> this in the console:
> mali-c55 16080000.isp: Detected Mali-C55 ISP 9000043.31032022.0
>
> This was done in order to enable booting mainline with mainline
> device trees.
>
> Assisted-by: LLM
> Signed-off-by: Linus Walleij <linusw@kernel.org>

Rob ACKed the final DT bindings on this v3 patch series so maybe you
can apply it?

Yours,
Linus Walleij

Re: [PATCH v3 1/5] dt-bindings: media: renesas,r9a09g057-ivc: Describe additional interrupts

[Lad, Prabhakar]

Hi Linus,

Thank you for the patch.

On Mon, Sep 28, 2026 at 1:32 PM Linus Walleij <linusw@kernel.org> wrote:
>
> The RZ/V2H IVC provides input frame-start and frame-stop completion
> interrupts alongside its input frame-end interrupt.
>
> Describe these optional interrupts, keeping frame end first and requiring
> only that entry to preserve support for existing device trees. Extend the
> example to show all three interrupts using mock interrupt numbers.
>
> Assisted-by: LLM
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Linus Walleij <linusw@kernel.org>
> ---
>  .../devicetree/bindings/media/renesas,r9a09g057-ivc.yaml      | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml b/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml
> index c09cbd8c9e35..3eeb1a92c9cf 100644
> --- a/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml
> +++ b/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml
> @@ -21,7 +21,11 @@ properties:
>      maxItems: 1
>
>    interrupts:
> -    maxItems: 1
> +    minItems: 1
> +    items:
> +      - description: Image input frame-end interrupt
> +      - description: Image input frame-start interrupt
> +      - description: Frame-stop processing completion interrupt
>
>    clocks:
>      items:
> @@ -92,7 +96,10 @@ examples:
>                 <&cpg 0xd3>;
>        reset-names = "reg", "axi", "isp";
>
> -      interrupts = <GIC_SPI 861 IRQ_TYPE_EDGE_RISING>;
> +      /* Example interrupt numbers. */
> +      interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>,
> +                   <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>,
> +                   <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
>
I think it would be better to use the actual interrupt numbers used on
the RZ/V2H(P) SoC. Most of the Renesas bindings use the actual
interrupt numbers.

Rest LGTM,
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Cheers,
Prabhakar

>        port {
>          ivc_out: endpoint {
>
> --
> 2.55.0
>
>

Re: [PATCH v3 2/5] dt-bindings: media: arm,mali-c55: Describe DMA line-tick interrupts

[Lad, Prabhakar]

Hi Linus,

Thank you for the patch.

On Mon, Sep 28, 2026 at 1:42 PM Linus Walleij <linusw@kernel.org> wrote:
>
> Mali-C55 exposes separate full-resolution and UV DMA writer line-tick
> interrupts in addition to its combined core interrupt.
>
> Describe these optional interrupts, keeping the core interrupt first and
> requiring only that entry to preserve support for existing device trees.
> Extend the example to show all three interrupts using mock interrupt
> numbers.
>
> Assisted-by: LLM
> Signed-off-by: Linus Walleij <linusw@kernel.org>
> ---
>  Documentation/devicetree/bindings/media/arm,mali-c55.yaml | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/media/arm,mali-c55.yaml b/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
> index fc4fcd19922a..8fcc46660b75 100644
> --- a/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
> +++ b/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
> @@ -18,7 +18,11 @@ properties:
>      maxItems: 1
>
>    interrupts:
> -    maxItems: 1
> +    minItems: 1
> +    items:
> +      - description: Combined ISP core interrupt
> +      - description: Full-resolution DMA writer line-tick interrupt
> +      - description: Full-resolution UV DMA writer line-tick interrupt
>
>    clocks:
>      items:
> @@ -75,7 +79,10 @@ examples:
>        clock-names = "vclk", "aclk", "hclk";
>        resets = <&resets 0>, <&resets 1>, <&resets 2>;
>        reset-names = "vresetn", "aresetn", "hresetn";
> -      interrupts = <GIC_SPI 861 IRQ_TYPE_EDGE_RISING>;
> +      /* Example interrupt numbers. */
> +      interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> +                   <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>,
> +                   <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
>
Same comment as patch 1/4.

Rest LGTM,
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Cheers,
Prabhakar

>        port {
>          isp_in: endpoint {
>
> --
> 2.55.0
>
>

Re: [PATCH v3 3/5] dt-bindings: media: arm,mali-c55: Add power domain

[Lad, Prabhakar]

On Mon, Sep 28, 2026 at 1:54 PM Linus Walleij <linusw@kernel.org> wrote:
>
> Some Mali-C55 integrations place the ISP in a power domain. In
> particular, RZ/V2H uses the CPG domain to manage its module clocks
> through runtime PM.
>
> Allow a single power domain and describe it in the example. Keep the
> property optional for integrations that do not expose a power domain.
>
> Assisted-by: LLM
> Signed-off-by: Linus Walleij <linusw@kernel.org>
> ---
>  Documentation/devicetree/bindings/media/arm,mali-c55.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Cheers,
Prabhakar

> diff --git a/Documentation/devicetree/bindings/media/arm,mali-c55.yaml b/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
> index 8fcc46660b75..3a11d3f8488a 100644
> --- a/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
> +++ b/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
> @@ -36,6 +36,9 @@ properties:
>        - const: aclk
>        - const: hclk
>
> +  power-domains:
> +    maxItems: 1
> +
>    resets:
>      items:
>        - description: vclk domain reset
> @@ -77,6 +80,7 @@ examples:
>        reg = <0x400000 0x200000>;
>        clocks = <&clk 0>, <&clk 1>, <&clk 2>;
>        clock-names = "vclk", "aclk", "hclk";
> +      power-domains = <&power>;
>        resets = <&resets 0>, <&resets 1>, <&resets 2>;
>        reset-names = "vresetn", "aresetn", "hresetn";
>        /* Example interrupt numbers. */
>
> --
> 2.55.0
>
>

Re: [PATCH v3 5/5] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add ISP and IVC nodes

[Lad, Prabhakar]

Hi Linus,

On Mon, Sep 28, 2026 at 1:33 PM Linus Walleij <linusw@kernel.org> wrote:
>
> From: Daniel Scally <dan.scally@ideasonboard.com>
>
> Add nodes to devicetree enabling the ISP and IVC that are found on
> the RZ/V2H(P) SoC.
>
> [Rebase onto v7.3-rc1 and sort the board overrides by label.
>  - Linus Walleij]
>
> Assisted-by: LLM
> Signed-off-by: Daniel Scally <dan.scally@ideasonboard.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Linus Walleij <linusw@kernel.org>
> ---
>  arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
> index 637fc92dcc26..74b75be599ae 100644
> --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
> +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
> @@ -305,6 +305,14 @@ versa3: clock-generator@69 {
>         };
>  };
>
> +&isp {
> +       status = "okay";
> +};
> +
> +&ivc {
> +       status = "okay";
> +};
> +
I was trying this on 20261006 as soon as I start camshark I get the
output below. Im using IMX708 sensor on the RZ/V2H EVK. Are there any
additional patches required for this to work (any sepcific version of
v4l-utils/libcamera) ?

192 login: [  196.846011] rcu: INFO: rcu_preempt detected stalls on CPUs/tasks:
[  196.852193] rcu:     3-...0: (8 ticks this GP)
idle=2de4/1/0x4000000000000000 softirq=3984/3985 fqs=1048
[  196.861489] rcu:     (detected by 2, t=5253 jiffies, g=5753, q=6 ncpus=4)
[  206.875392] rcu: rcu_preempt kthread timer wakeup didn't happen for
1254 jiffies! g5753 f0x0 RCU_GP_WAIT_FQS(5) ->state=I
[  206.886411] rcu:     Possible timer handling issue on cpu=2
timer-softirq=2740
[  206.893406] rcu: rcu_preempt kthread starved for 1255 jiffies!
g5753 f0x0 RCU_GP_WAIT_FQS(5) ->state=I ->cpu=2
[  206.903455] rcu:     Unless rcu_preempt kthread gets sufficient CPU
time, OOM is now expected behavior.
[  206.912616] rcu: RCU grace-period kthread stack dump:
[  206.918235] rcu: Stack dump where RCU GP kthread last ran:
[  178.982667] rcu: INFO: rcu_preempt detected stalls on CPUs/tasks:
[  178.988821] rcu:     3-...0: (8 ticks this GP)
idle=2de4/1/0x4000000000000000 softirq=3984/3985 fqs=3946
[  178.998117] rcu:     (detected by 2, t=22262 jiffies, g=5753, q=6 ncpus=4)
[  199.056986] rcu: INFO: rcu_preempt detected stalls on CPUs/tasks:
[  199.063092] rcu:     3-...0: (8 ticks this GP)
idle=2de4/1/0x4000000000000000 softirq=3984/3985 fqs=6596
[  199.072322] rcu:     (detected by 2, t=38018 jiffies, g=5753, q=69 ncpus=4)
[  176.177639] rcu: INFO: rcu_preempt detected stalls on CPUs/tasks:
[  176.183749] rcu:     3-...0: (8 ticks this GP)
idle=2de4/1/0x4000000000000000 softirq=3984/3985 fqs=9246
[  176.192984] rcu:     (detected by 2, t=53773 jiffies, g=5753, q=70 ncpus=4)


Cheers,
Prabhakar

>  &mdio0 {
>         phy0: ethernet-phy@0 {
>                 compatible = "ethernet-phy-id0022.1640";
>
> --
> 2.55.0
>
>

Re: [PATCH v3 1/5] dt-bindings: media: renesas,r9a09g057-ivc: Describe additional interrupts

[Dan Scally]

Hi Linus

On 28/09/2026 13:21, Linus Walleij wrote:
> The RZ/V2H IVC provides input frame-start and frame-stop completion
> interrupts alongside its input frame-end interrupt.
> 
> Describe these optional interrupts, keeping frame end first and requiring
> only that entry to preserve support for existing device trees. Extend the
> example to show all three interrupts using mock interrupt numbers.
> 
> Assisted-by: LLM
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Linus Walleij <linusw@kernel.org>
> ---
>   .../devicetree/bindings/media/renesas,r9a09g057-ivc.yaml      | 11 +++++++++--
>   1 file changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml b/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml
> index c09cbd8c9e35..3eeb1a92c9cf 100644
> --- a/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml
> +++ b/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml
> @@ -21,7 +21,11 @@ properties:
>       maxItems: 1
>   
>     interrupts:
> -    maxItems: 1
> +    minItems: 1
> +    items:
> +      - description: Image input frame-end interrupt
> +      - description: Image input frame-start interrupt
> +      - description: Frame-stop processing completion interrupt

Perhaps interrupt-names too?

Thanks
Dan

>   
>     clocks:
>       items:
> @@ -92,7 +96,10 @@ examples:
>                  <&cpg 0xd3>;
>         reset-names = "reg", "axi", "isp";
>   
> -      interrupts = <GIC_SPI 861 IRQ_TYPE_EDGE_RISING>;
> +      /* Example interrupt numbers. */
> +      interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>,
> +                   <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>,
> +                   <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
>   
>         port {
>           ivc_out: endpoint {
> 

Re: [PATCH v3 2/5] dt-bindings: media: arm,mali-c55: Describe DMA line-tick interrupts

[Dan Scally]

Hi Linus

On 28/09/2026 13:21, Linus Walleij wrote:
> Mali-C55 exposes separate full-resolution and UV DMA writer line-tick
> interrupts in addition to its combined core interrupt.
> 
> Describe these optional interrupts, keeping the core interrupt first and
> requiring only that entry to preserve support for existing device trees.
> Extend the example to show all three interrupts using mock interrupt
> numbers.
> 
> Assisted-by: LLM
> Signed-off-by: Linus Walleij <linusw@kernel.org>
> ---
>   Documentation/devicetree/bindings/media/arm,mali-c55.yaml | 11 +++++++++--
>   1 file changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/media/arm,mali-c55.yaml b/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
> index fc4fcd19922a..8fcc46660b75 100644
> --- a/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
> +++ b/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
> @@ -18,7 +18,11 @@ properties:
>       maxItems: 1
>   
>     interrupts:
> -    maxItems: 1
> +    minItems: 1
> +    items:
> +      - description: Combined ISP core interrupt
> +      - description: Full-resolution DMA writer line-tick interrupt
> +      - description: Full-resolution UV DMA writer line-tick interrupt

As with the IVC, perhaps an interrupt-names entry would also be useful?

Thanks
Dan

>   
>     clocks:
>       items:
> @@ -75,7 +79,10 @@ examples:
>         clock-names = "vclk", "aclk", "hclk";
>         resets = <&resets 0>, <&resets 1>, <&resets 2>;
>         reset-names = "vresetn", "aresetn", "hresetn";
> -      interrupts = <GIC_SPI 861 IRQ_TYPE_EDGE_RISING>;
> +      /* Example interrupt numbers. */
> +      interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> +                   <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>,
> +                   <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
>   
>         port {
>           isp_in: endpoint {
> 

Re: [PATCH v3 3/5] dt-bindings: media: arm,mali-c55: Add power domain

[Dan Scally]

Hi Linus

On 28/09/2026 13:21, Linus Walleij wrote:
> Some Mali-C55 integrations place the ISP in a power domain. In
> particular, RZ/V2H uses the CPG domain to manage its module clocks
> through runtime PM.
> 
> Allow a single power domain and describe it in the example. Keep the
> property optional for integrations that do not expose a power domain.
> 
> Assisted-by: LLM
> Signed-off-by: Linus Walleij <linusw@kernel.org>
> ---

Reviewed-by: Daniel Scally <dan.scally@ideasonboard.com>

>   Documentation/devicetree/bindings/media/arm,mali-c55.yaml | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/media/arm,mali-c55.yaml b/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
> index 8fcc46660b75..3a11d3f8488a 100644
> --- a/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
> +++ b/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
> @@ -36,6 +36,9 @@ properties:
>         - const: aclk
>         - const: hclk
>   
> +  power-domains:
> +    maxItems: 1
> +
>     resets:
>       items:
>         - description: vclk domain reset
> @@ -77,6 +80,7 @@ examples:
>         reg = <0x400000 0x200000>;
>         clocks = <&clk 0>, <&clk 1>, <&clk 2>;
>         clock-names = "vclk", "aclk", "hclk";
> +      power-domains = <&power>;
>         resets = <&resets 0>, <&resets 1>, <&resets 2>;
>         reset-names = "vresetn", "aresetn", "hresetn";
>         /* Example interrupt numbers. */
> 

Re: [PATCH v3 5/5] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add ISP and IVC nodes

[Linus Walleij]

Hi Prabhakar,

On Tue, Oct 6, 2026 at 8:33 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:

> I was trying this on 20261006 as soon as I start camshark I get the
> output below. Im using IMX708 sensor on the RZ/V2H EVK. Are there any
> additional patches required for this to work (any sepcific version of
> v4l-utils/libcamera) ?

Do you also have these patches queued as fixes?
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/log/drivers/media/platform/arm/mali-c55

Yours,
Linus Walleij

Re: [PATCH v3 2/5] dt-bindings: media: arm,mali-c55: Describe DMA line-tick interrupts

[Linus Walleij]

On Wed, Oct 7, 2026 at 12:49 PM Dan Scally <dan.scally@ideasonboard.com> wrote:

> >     interrupts:
> > -    maxItems: 1
> > +    minItems: 1
> > +    items:
> > +      - description: Combined ISP core interrupt
> > +      - description: Full-resolution DMA writer line-tick interrupt
> > +      - description: Full-resolution UV DMA writer line-tick interrupt
>
> As with the IVC, perhaps an interrupt-names entry would also be useful?

I think interrupt-names are only used if you have say 100
possible interrupts and only want to specify 2. So you can
look up the 2 you need by name.

I don't see any situation where sparse interrupt supply
would be applicable for this IP? It's just 3 of them.

(But let's allow the DT binding maintainers an opportunity
to slap me on the fingers about this one...)

Yours,
Linus Walleij