Re: [PATCH v2 1/4] dt-bindings: clock: qcom,sm8450-videocc: Fix clock inputs for Glymur

["Rob Herring (Arm)" <robh@kernel.org>]

On Thu, 08 Oct 2026 16:10:33 +0800, Shawn Guo wrote:
> The schema describes exactly two clock inputs for every compatible it
> covers, a board XO and a video AHB clock from GCC. That does not match
> the video clock controller found on Glymur, Nord and SM8750.
> 
> Per the hardware documentation, the controller on these SoCs has three
> clock inputs: the board XO, the always-on board XO that feeds its PLL
> reference, and the 32 kHz chip sleep clock that sources its sleep clock
> generator. It has no AHB clock input. The AHB clock the controller uses
> for itself is generated inside the block from the XO input.
> 
> Because the schema stops at two items, the sleep clock input cannot be
> described in device tree at all, and the second item is described as a
> clock that is not routed into the controller.
> 
> Describe three inputs for the Glymur, Nord and SM8750 compatibles and
> keep the existing two-input description for the remaining compatibles.
> 
> Assisted-by: LLM
> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> ---
>  .../bindings/clock/qcom,sm8450-videocc.yaml   | 26 ++++++++++++++++---
>  1 file changed, 23 insertions(+), 3 deletions(-)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>