Re: [PATCH] arm64: dts: qcom: shikra: Switch CPU ETMs to MMIO-based probing

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 10/14/26 10:19 AM, Jie Gan wrote:
> 
> 
> On 10/13/2026 8:38 PM, Konrad Dybcio wrote:
>> On 9/22/26 5:09 AM, Jie Gan wrote:
>>> The etm0-etm3 nodes are declared with "arm,coresight-etm4x-sysreg"
>>> but do not implement self-hosted system-register trace access on
>>> this SoC: ID_AA64DFR0_EL1.TraceVer reads as 0 on the affected CPUs,
>>> so etm4_init_sysreg_access() correctly reports the access mechanism
>>> as unavailable and the ETMv4 driver fails to probe with -EINVAL.
>>>
>>> The CPU ETMs have a memory-mapped aperture, so switch each node to
>>> the standard "arm,coresight-etm4x", "arm,primecell" compatible with
>>> its MMIO reg range.
>>>
>>> Fixes: eed738c6dd0c ("arm64: dts: qcom: shikra: Add coresight nodes")
>>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>>> ---
>>
>> Do we still need qcom,skip-power-up on new SoCs *with* MMIO access?
>>
> 
> Yes, we need qcom,skip-power-up for all ETM device with or w/o MMIO access.
> 
>> GPT has concerns regarding whether we need to add
>> arm,coresight-loses-context-with-cpu>
> 
> This logic to be handled by HYP on Shikra SoC, so I didnt enable it in kernel.

https://lore.kernel.org/linux-arm-msm/20261005-shikra-el2-v3-0-618f7343695c@oss.qualcomm.com/

We're going to, in parallel, ship Shikra without the Qualcomm
hypervisor so please keep that in mind. Should the submitters of the
non-Gunyah overlay add these properties there as they respin? Does
that concern all Coresight components?

Konrad