Re: [PATCH] arm64: dts: qcom: shikra: Switch CPU ETMs to MMIO-based probing

[Jie Gan <jie.gan@oss.qualcomm.com>]

On 9/22/2026 11:17 AM, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] arm64: dts: shikra: missing arm,coresight-loses-context-with-cpu property
> --
> 
> commit aab8605634d60b3bebc7a736fcec36f07d87f859
> Author: Jie Gan <jie.gan@oss.qualcomm.com>
> 
> arm64: dts: qcom: shikra: Switch CPU ETMs to MMIO-based probing
> 
> The etm0-etm3 nodes are declared with "arm,coresight-etm4x-sysreg"
> but do not implement self-hosted system-register trace access on
> this SoC. The CPU ETMs have a memory-mapped aperture, so switch each
> node to the standard "arm,coresight-etm4x", "arm,primecell" compatible
> with its MMIO reg range.
> 
>> diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
>> index c1f06f692f664..62bacf749241f 100644
>> --- a/arch/arm64/boot/dts/qcom/shikra.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
> [ ... ]
>> @@ -3218,6 +3150,24 @@ cti@9020000 {
>>   			label = "cti_apss_pe0";
>>   		};
>>   
>> +		etm@9040000 {
>> +			compatible = "arm,coresight-etm4x", "arm,primecell";
> 
 > [Severity: Medium]> Will this omission cause ETM tracing to silently 
stop functioning during CPU
> deep idle?
> 
> By switching to MMIO without adding the arm,coresight-loses-context-with-cpu
> property, the coresight driver will skip allocating the save state.
> 
> drivers/hwtracing/coresight/coresight-etm4x-core.c:etm4_add_coresight_dev() {
>      ...
>      else if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
>          pm_save = coresight_loses_context_with_cpu(dev);
>      ...
> }

Currently, we are not enabling the CPU SAVE/RESTORE in HLOS driver on 
QCOM platforms.

Thanks,
Jie

> 
> Should the arm,coresight-loses-context-with-cpu property be added to these
> new MMIO etm nodes?
>