* [PATCH] arm64: dts: qcom: shikra: Switch CPU ETMs to MMIO-based probing
@ 2026-09-22 3:09 Jie Gan
2026-09-22 3:17 ` sashiko-bot
0 siblings, 1 reply; 3+ messages in thread
From: Jie Gan @ 2026-09-22 3:09 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Abel Vesa, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jie Gan
Cc: Konrad Dybcio, linux-arm-msm, devicetree, linux-kernel, Jie Gan
The etm0-etm3 nodes are declared with "arm,coresight-etm4x-sysreg"
but do not implement self-hosted system-register trace access on
this SoC: ID_AA64DFR0_EL1.TraceVer reads as 0 on the affected CPUs,
so etm4_init_sysreg_access() correctly reports the access mechanism
as unavailable and the ETMv4 driver fails to probe with -EINVAL.
The CPU ETMs have a memory-mapped aperture, so switch each node to
the standard "arm,coresight-etm4x", "arm,primecell" compatible with
its MMIO reg range.
Fixes: eed738c6dd0c ("arm64: dts: qcom: shikra: Add coresight nodes")
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
Signed-off-by: Jie Gan <jiegan@qti.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 140 ++++++++++++++++++-----------------
1 file changed, 72 insertions(+), 68 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index c1f06f692f66..62bacf749241 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -164,74 +164,6 @@ eud_in: endpoint {
};
};
- etm0 {
- compatible = "arm,coresight-etm4x-sysreg";
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
- clock-names = "apb_pclk";
- cpu = <&cpu0>;
- qcom,skip-power-up;
-
- out-ports {
- port {
- etm0_out: endpoint {
- remote-endpoint = <&funnel_cpuss0_in0>;
- };
- };
- };
- };
-
- etm1 {
- compatible = "arm,coresight-etm4x-sysreg";
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
- clock-names = "apb_pclk";
- cpu = <&cpu1>;
- qcom,skip-power-up;
-
- out-ports {
- port {
- etm1_out: endpoint {
- remote-endpoint = <&funnel_cpuss0_in1>;
- };
- };
- };
- };
-
- etm2 {
- compatible = "arm,coresight-etm4x-sysreg";
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
- clock-names = "apb_pclk";
- cpu = <&cpu2>;
- qcom,skip-power-up;
-
- out-ports {
- port {
- etm2_out: endpoint {
- remote-endpoint = <&funnel_cpuss0_in2>;
- };
- };
- };
- };
-
- etm3 {
- compatible = "arm,coresight-etm4x-sysreg";
-
- clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
- clock-names = "apb_pclk";
- cpu = <&cpu3>;
- qcom,skip-power-up;
-
- out-ports {
- port {
- etm3_out: endpoint {
- remote-endpoint = <&funnel_cpuss0_in3>;
- };
- };
- };
- };
-
firmware {
scm {
compatible = "qcom,scm-shikra", "qcom,scm";
@@ -3218,6 +3150,24 @@ cti@9020000 {
label = "cti_apss_pe0";
};
+ etm@9040000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x0 0x09040000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu0>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint = <&funnel_cpuss0_in0>;
+ };
+ };
+ };
+ };
+
cti@90e0000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x090e0000 0x0 0x1000>;
@@ -3236,6 +3186,24 @@ cti@9120000 {
label = "cti_apss_pe1";
};
+ etm@9140000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x0 0x09140000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu1>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint = <&funnel_cpuss0_in1>;
+ };
+ };
+ };
+ };
+
cti@9220000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x09220000 0x0 0x1000>;
@@ -3245,6 +3213,24 @@ cti@9220000 {
label = "cti_apss_pe2";
};
+ etm@9240000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x0 0x09240000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu2>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint = <&funnel_cpuss0_in2>;
+ };
+ };
+ };
+ };
+
cti@9320000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x09320000 0x0 0x1000>;
@@ -3254,6 +3240,24 @@ cti@9320000 {
label = "cti_apss_pe3";
};
+ etm@9340000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x0 0x09340000 0x0 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu3>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint = <&funnel_cpuss0_in3>;
+ };
+ };
+ };
+ };
+
funnel@9800000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x09800000 0x0 0x1000>;
---
base-commit: 5c4d4169604b335c38bbc79bc1fc03042981fc6f
change-id: 20260922-fix-etm-probe-issue-on-shikra-5a624f583975
Best regards,
--
Jie Gan <jie.gan@oss.qualcomm.com>
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] arm64: dts: qcom: shikra: Switch CPU ETMs to MMIO-based probing
2026-09-22 3:09 [PATCH] arm64: dts: qcom: shikra: Switch CPU ETMs to MMIO-based probing Jie Gan
@ 2026-09-22 3:17 ` sashiko-bot
2026-09-22 3:27 ` Jie Gan
0 siblings, 1 reply; 3+ messages in thread
From: sashiko-bot @ 2026-09-22 3:17 UTC (permalink / raw)
To: Jie Gan; +Cc: robh, devicetree, conor+dt
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] arm64: dts: shikra: missing arm,coresight-loses-context-with-cpu property
--
commit aab8605634d60b3bebc7a736fcec36f07d87f859
Author: Jie Gan <jie.gan@oss.qualcomm.com>
arm64: dts: qcom: shikra: Switch CPU ETMs to MMIO-based probing
The etm0-etm3 nodes are declared with "arm,coresight-etm4x-sysreg"
but do not implement self-hosted system-register trace access on
this SoC. The CPU ETMs have a memory-mapped aperture, so switch each
node to the standard "arm,coresight-etm4x", "arm,primecell" compatible
with its MMIO reg range.
> diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
> index c1f06f692f664..62bacf749241f 100644
> --- a/arch/arm64/boot/dts/qcom/shikra.dtsi
> +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
[ ... ]
> @@ -3218,6 +3150,24 @@ cti@9020000 {
> label = "cti_apss_pe0";
> };
>
> + etm@9040000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
[Severity: Medium]
Will this omission cause ETM tracing to silently stop functioning during CPU
deep idle?
By switching to MMIO without adding the arm,coresight-loses-context-with-cpu
property, the coresight driver will skip allocating the save state.
drivers/hwtracing/coresight/coresight-etm4x-core.c:etm4_add_coresight_dev() {
...
else if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
pm_save = coresight_loses_context_with_cpu(dev);
...
}
Should the arm,coresight-loses-context-with-cpu property be added to these
new MMIO etm nodes?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260922-fix-etm-probe-issue-on-shikra-v1-1-56d25e9bbe17@oss.qualcomm.com?part=1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] arm64: dts: qcom: shikra: Switch CPU ETMs to MMIO-based probing
2026-09-22 3:17 ` sashiko-bot
@ 2026-09-22 3:27 ` Jie Gan
0 siblings, 0 replies; 3+ messages in thread
From: Jie Gan @ 2026-09-22 3:27 UTC (permalink / raw)
To: sashiko-reviews; +Cc: robh, devicetree, conor+dt
On 9/22/2026 11:17 AM, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] arm64: dts: shikra: missing arm,coresight-loses-context-with-cpu property
> --
>
> commit aab8605634d60b3bebc7a736fcec36f07d87f859
> Author: Jie Gan <jie.gan@oss.qualcomm.com>
>
> arm64: dts: qcom: shikra: Switch CPU ETMs to MMIO-based probing
>
> The etm0-etm3 nodes are declared with "arm,coresight-etm4x-sysreg"
> but do not implement self-hosted system-register trace access on
> this SoC. The CPU ETMs have a memory-mapped aperture, so switch each
> node to the standard "arm,coresight-etm4x", "arm,primecell" compatible
> with its MMIO reg range.
>
>> diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
>> index c1f06f692f664..62bacf749241f 100644
>> --- a/arch/arm64/boot/dts/qcom/shikra.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
> [ ... ]
>> @@ -3218,6 +3150,24 @@ cti@9020000 {
>> label = "cti_apss_pe0";
>> };
>>
>> + etm@9040000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>
> [Severity: Medium]> Will this omission cause ETM tracing to silently
stop functioning during CPU
> deep idle?
>
> By switching to MMIO without adding the arm,coresight-loses-context-with-cpu
> property, the coresight driver will skip allocating the save state.
>
> drivers/hwtracing/coresight/coresight-etm4x-core.c:etm4_add_coresight_dev() {
> ...
> else if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
> pm_save = coresight_loses_context_with_cpu(dev);
> ...
> }
Currently, we are not enabling the CPU SAVE/RESTORE in HLOS driver on
QCOM platforms.
Thanks,
Jie
>
> Should the arm,coresight-loses-context-with-cpu property be added to these
> new MMIO etm nodes?
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2026-09-22 3:09 [PATCH] arm64: dts: qcom: shikra: Switch CPU ETMs to MMIO-based probing Jie Gan
2026-09-22 3:17 ` sashiko-bot
2026-09-22 3:27 ` Jie Gan
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