From: "Xuyang Dong" <dongxuyang@eswincomputing.com>
To: "Krzysztof Kozlowski" <krzk@kernel.org>
Cc: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, ben-linux@fluff.org,
ben.dooks@codethink.co.uk, p.zabel@pengutronix.de,
linux-pwm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, ningyu@eswincomputing.com,
linmin@eswincomputing.com, xuxiang@eswincomputing.com,
wangguosheng@eswincomputing.com, pinkesh.vaghela@einfochips.com
Subject: Re: Re: [PATCH v6 1/2] dt-bindings: pwm: dwc: add optional reset
Date: Wed, 29 Apr 2026 17:30:00 +0800 (GMT+08:00) [thread overview]
Message-ID: <1ac7fae4.5c66.19dd892ec4d.Coremail.dongxuyang@eswincomputing.com> (raw)
In-Reply-To: <7bd6129a-dd37-48e8-a54c-cc149a2b84a2@kernel.org>
> >>>
> >>> +allOf:
> >>> + - $ref: pwm.yaml#
> >>> +
> >>> + - if:
> >>> + properties:
> >>> + compatible:
> >>> + contains:
> >>> + const: eswin,eic7700-pwm
> >>
> >> Same problem as v3 which I commented. I do not understand why your new
> >> device has also 1 reset.
> >>
> >> Your commit msg MUST explain why 1 reset is valid.
> >>
> >
> > Hi Krzysztof,
> >
> > Although the PWM IP supports two clock domains, each requiring a reset,
> > the EIC7700 implementation uses the same clock domain for both clock
> > signals. Therefore, the eic7700-pwm only supports one reset.
> >
>
> If we speak about eic7700, explain why it has two resets now, according
> to schema, even though you say it has not.
>
> But I was speaking about dw-apb-timers-pwm, which has one reset as well!
> Why you are not having proper constraints? Please read writing bindings
> document.
>
Hi Krzysztof,
Let me clarify the reset signals.
- snps,dw-apb-timers-pwm2: IP spec has 2 optional reset signals (one per
clock domain), SoC vendor decides whether to wire them — so maxItems: 2,
optional in required.
- eswin,eic7700-pwm: SoC physically ties both signals to one reset — so
exactly 1, required.
So I think the correct patch should be like this:
Modify the commit message as follows:
The DesignWare PWM IP has up to two optional reset signals, one per clock
domain (presetn for pclk, timer_N_resetn for timer_N_clk).
SoC vendors decides to wire them, so maxItems: 2 is the upper bound for
the generic snps,dw-apb-timers-pwm2 compatible.
The ESWIN EIC7700 ties both reset domains to a single physical reset
signal, so exactly one reset is required. Add maxItems: 1 to the if-then
block for eswin,eic7700-pwm to enforce this.
Modify the YAML as follows:
-allOf:
- - $ref: pwm.yaml#
-
properties:
compatible:
- const: snps,dw-apb-timers-pwm2
+ enum:
+ - snps,dw-apb-timers-pwm2
+ - eswin,eic7700-pwm
reg:
maxItems: 1
@@ -43,6 +42,13 @@ properties:
- const: bus
- const: timer
+ resets:
+ minItems: 1
+ maxItems: 2
+
snps,pwm-number:
$ref: /schemas/types.yaml#/definitions/uint32
description: The number of PWM channels configured for this instance
@@ -54,6 +60,21 @@ required:
- clocks
- clock-names
+allOf:
+ - $ref: pwm.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: eswin,eic7700-pwm
+ then:
+ properties:
+ resets:
+ maxItems: 1
+ required:
+ - resets
+
additionalProperties: false
Do you think this modification is more appropriate?
Best regards,
Xuyang Dong
next prev parent reply other threads:[~2026-04-29 9:30 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-24 9:45 [PATCH v6 0/2] Update designware pwm driver dongxuyang
2026-04-24 9:54 ` [PATCH v6 1/2] dt-bindings: pwm: dwc: add optional reset dongxuyang
2026-04-24 17:03 ` Conor Dooley
2026-04-28 8:42 ` Krzysztof Kozlowski
2026-04-28 9:30 ` Xuyang Dong
2026-04-28 9:34 ` Krzysztof Kozlowski
2026-04-29 9:30 ` Xuyang Dong [this message]
2026-04-24 9:57 ` [PATCH v6 2/2] pwm: dwc: add of/platform support dongxuyang
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