[PATCH v6 0/2] dma: arm-dma350: handle shared channel IRQ wiring on sky1

[PATCH v6 0/2] dma: arm-dma350: handle shared channel IRQ wiring on sky1

[Jun Guo]

This series updates DMA-350 support for the SKY1 integration where all DMA
channel interrupt outputs are wired to the same GIC SPI.

Patch 1 enables DMANSECCTRL.INTREN_ANYCHINTR in the driver so per-channel
interrupt status is propagated even when channels share one parent IRQ
line.

Patch 2 adds the SKY1 DMA-350 DT node and describes the channel interrupt
sources using 8 channel entries, while all entries map to the same SPI.

Tested on CIX SKY1 with dmatest:
  % echo 2000 > /sys/module/dmatest/parameters/timeout
  % echo 1 > /sys/module/dmatest/parameters/iterations
  % echo "" > /sys/module/dmatest/parameters/channel
  % echo 1 > /sys/module/dmatest/parameters/run

Changes in v6:
- Drop the dt-binding update and keep the existing 8-channel interrupt
 schema.
- Simplify driver change to a minimal fix:
 enable DMANSECCTRL.INTREN_ANYCHINTR.
- Update SKY1 DT node to describe 8 channel interrupt entries mapped
 to one SPI.

Changes in v5:
- Fix the formatting issue in the AI tag.
- Remove the unnecessary "cix,sky1-dma-350".

Changes in v4:
- Reword binding text to align with kernel style.
- Revise the AI attribution to the standard format.
- Remove redundant links from the commit log.

Changes in v3:
- Rework binding compatible description to match generic-first model.
- Keep interrupts schema support for both 1-IRQ and 8-IRQ topologies.
- Drop SoC match-data dependency for IRQ mode selection.
- Detect IRQ topology via platform_irq_count() in probe path.
- Refactor IRQ handling into a shared channel handler.
- Enable DMANSECCTRL.INTREN_ANYCHINTR only in combined IRQ mode.

Changes in v2:
- Update to kernel standards, enhance patch description, and refactor
 driver to use match data for hardware differentiation instead of
 compatible strings.

Jun Guo (2):
  dma: arm-dma350: enable ANYCH interrupt for shared IRQ wiring
  arm64: dts: cix: add sky1 DMA-350 node with channel IRQ entries

 arch/arm64/boot/dts/cix/sky1.dtsi | 14 ++++++++++++++
 drivers/dma/arm-dma350.c          |  9 +++++++++
 2 files changed, 23 insertions(+)

-- 
2.34.1

[PATCH v6 1/2] dma: arm-dma350: enable ANYCH interrupt for shared IRQ wiring

[Jun Guo]

Enable DMANSECCTRL.INTREN_ANYCHINTR during probe so channel
interrupts are propagated when integrators wire DMA-350 channels
onto a shared IRQ line.

Signed-off-by: Jun Guo <jun.guo@cixtech.com>
---
 drivers/dma/arm-dma350.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c
index 84220fa83029..09403aca8bb0 100644
--- a/drivers/dma/arm-dma350.c
+++ b/drivers/dma/arm-dma350.c
@@ -13,6 +13,11 @@
 #include "dmaengine.h"
 #include "virt-dma.h"
 
+#define DMANSECCTRL		0x200
+
+#define NSEC_CTRL		0x0c
+#define INTREN_ANYCHINTR_EN	BIT(0)
+
 #define DMAINFO			0x0f00
 
 #define DMA_BUILDCFG0		0xb0
@@ -582,6 +587,10 @@ static int d350_probe(struct platform_device *pdev)
 	dmac->dma.device_issue_pending = d350_issue_pending;
 	INIT_LIST_HEAD(&dmac->dma.channels);
 
+	reg = readl_relaxed(base + DMANSECCTRL + NSEC_CTRL);
+	writel_relaxed(reg | INTREN_ANYCHINTR_EN,
+		       base + DMANSECCTRL + NSEC_CTRL);
+
 	/* Would be nice to have per-channel caps for this... */
 	memset = true;
 	for (int i = 0; i < nchan; i++) {
-- 
2.34.1

Re: [PATCH v6 1/2] dma: arm-dma350: enable ANYCH interrupt for shared IRQ wiring

[Jun Guo]

Hi Robin,

Just pinging. I’d like to ask if you have any comments on the latest patch?

On 3/25/2026 7:21 PM, Jun Guo wrote:
> Enable DMANSECCTRL.INTREN_ANYCHINTR during probe so channel
> interrupts are propagated when integrators wire DMA-350 channels
> onto a shared IRQ line.
> 
> Signed-off-by: Jun Guo <jun.guo@cixtech.com>
> ---
>   drivers/dma/arm-dma350.c | 9 +++++++++
>   1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c
> index 84220fa83029..09403aca8bb0 100644
> --- a/drivers/dma/arm-dma350.c
> +++ b/drivers/dma/arm-dma350.c
> @@ -13,6 +13,11 @@
>   #include "dmaengine.h"
>   #include "virt-dma.h"
>   
> +#define DMANSECCTRL		0x200
> +
> +#define NSEC_CTRL		0x0c
> +#define INTREN_ANYCHINTR_EN	BIT(0)
> +
>   #define DMAINFO			0x0f00
>   
>   #define DMA_BUILDCFG0		0xb0
> @@ -582,6 +587,10 @@ static int d350_probe(struct platform_device *pdev)
>   	dmac->dma.device_issue_pending = d350_issue_pending;
>   	INIT_LIST_HEAD(&dmac->dma.channels);
>   
> +	reg = readl_relaxed(base + DMANSECCTRL + NSEC_CTRL);
> +	writel_relaxed(reg | INTREN_ANYCHINTR_EN,
> +		       base + DMANSECCTRL + NSEC_CTRL);
> +
>   	/* Would be nice to have per-channel caps for this... */
>   	memset = true;
>   	for (int i = 0; i < nchan; i++) {

Re: [PATCH v6 1/2] dma: arm-dma350: enable ANYCH interrupt for shared IRQ wiring

[Frank Li]

On Tue, Apr 21, 2026 at 03:24:11PM +0800, Jun Guo wrote:
> Hi Robin,
>
> Just pinging. I’d like to ask if you have any comments on the latest patch?
>
> On 3/25/2026 7:21 PM, Jun Guo wrote:
> > Enable DMANSECCTRL.INTREN_ANYCHINTR during probe so channel
> > interrupts are propagated when integrators wire DMA-350 channels
> > onto a shared IRQ line.

Your tag is wrong

dmaegine: arm-dma350: enable ANYCH ...

> >
> > Signed-off-by: Jun Guo <jun.guo@cixtech.com>
> > ---
> >   drivers/dma/arm-dma350.c | 9 +++++++++
> >   1 file changed, 9 insertions(+)
> >
> > diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c
> > index 84220fa83029..09403aca8bb0 100644
> > --- a/drivers/dma/arm-dma350.c
> > +++ b/drivers/dma/arm-dma350.c
> > @@ -13,6 +13,11 @@
> >   #include "dmaengine.h"
> >   #include "virt-dma.h"

extra empty line between header file and macro


> > +#define DMANSECCTRL		0x200
> > +
> > +#define NSEC_CTRL		0x0c

why need two layer regiser define, your use DMANSECCTRL + NSEC_CTRL，

why not use one macro for 0x20c

Frank

> > +#define INTREN_ANYCHINTR_EN	BIT(0)
> > +
> >   #define DMAINFO			0x0f00
> >   #define DMA_BUILDCFG0		0xb0
> > @@ -582,6 +587,10 @@ static int d350_probe(struct platform_device *pdev)
> >   	dmac->dma.device_issue_pending = d350_issue_pending;
> >   	INIT_LIST_HEAD(&dmac->dma.channels);
> > +	reg = readl_relaxed(base + DMANSECCTRL + NSEC_CTRL);
> > +	writel_relaxed(reg | INTREN_ANYCHINTR_EN,
> > +		       base + DMANSECCTRL + NSEC_CTRL);
> > +
> >   	/* Would be nice to have per-channel caps for this... */
> >   	memset = true;
> >   	for (int i = 0; i < nchan; i++) {
>

Re: [PATCH v6 1/2] dma: arm-dma350: enable ANYCH interrupt for shared IRQ wiring

[Jun Guo]

On 4/22/2026 5:54 PM, Frank Li wrote:
> [Some people who received this message don't often get email from frank.li@nxp.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> 
> EXTERNAL EMAIL
> 
> On Tue, Apr 21, 2026 at 03:24:11PM +0800, Jun Guo wrote:
>> Hi Robin,
>>
>> Just pinging. I’d like to ask if you have any comments on the latest patch?
>>
>> On 3/25/2026 7:21 PM, Jun Guo wrote:
>>> Enable DMANSECCTRL.INTREN_ANYCHINTR during probe so channel
>>> interrupts are propagated when integrators wire DMA-350 channels
>>> onto a shared IRQ line.
> 
> Your tag is wrong
> 
> dmaegine: arm-dma350: enable ANYCH ...	
Okay, I'll fix this in the next version.

> 
>>>
>>> Signed-off-by: Jun Guo <jun.guo@cixtech.com>
>>> ---
>>>    drivers/dma/arm-dma350.c | 9 +++++++++
>>>    1 file changed, 9 insertions(+)
>>>
>>> diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c
>>> index 84220fa83029..09403aca8bb0 100644
>>> --- a/drivers/dma/arm-dma350.c
>>> +++ b/drivers/dma/arm-dma350.c
>>> @@ -13,6 +13,11 @@
>>>    #include "dmaengine.h"
>>>    #include "virt-dma.h"
> 
> extra empty line between header file and macro
The space actually exists in the code, but it is hidden in the review 
records.

> 
> 
>>> +#define DMANSECCTRL                0x200
>>> +
>>> +#define NSEC_CTRL          0x0c
> 
> why need two layer regiser define, your use DMANSECCTRL + NSEC_CTRL，
> 
> why not use one macro for 0x20c
> 
DMANSECCTRL is the base address for a set of control registers. 
Currently, only the NSEC_CTRL register within that set is being used. 
All other registers in the same group share this same base address, and 
a similar arrangement applies to DMAINFO.
> 
>>> +#define INTREN_ANYCHINTR_EN        BIT(0)
>>> +
>>>    #define DMAINFO                   0x0f00
>>>    #define DMA_BUILDCFG0             0xb0
>>> @@ -582,6 +587,10 @@ static int d350_probe(struct platform_device *pdev)
>>>      dmac->dma.device_issue_pending = d350_issue_pending;
>>>      INIT_LIST_HEAD(&dmac->dma.channels);
>>> +   reg = readl_relaxed(base + DMANSECCTRL + NSEC_CTRL);
>>> +   writel_relaxed(reg | INTREN_ANYCHINTR_EN,
>>> +                  base + DMANSECCTRL + NSEC_CTRL);
>>> +
>>>      /* Would be nice to have per-channel caps for this... */
>>>      memset = true;
>>>      for (int i = 0; i < nchan; i++) {
>>

[PATCH v6 2/2] arm64: dts: cix: add sky1 DMA-350 node with channel IRQ entries

[Jun Guo]

Describe the DMA-350 channel interrupt sources in DT using 8
interrupt entries, while all entries map to the same GIC SPI
as wired on this platform.

Signed-off-by: Jun Guo <jun.guo@cixtech.com>
---
 arch/arm64/boot/dts/cix/sky1.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
index 210739beac6d..ca3403df6e8b 100644
--- a/arch/arm64/boot/dts/cix/sky1.dtsi
+++ b/arch/arm64/boot/dts/cix/sky1.dtsi
@@ -480,6 +480,20 @@ iomuxc: pinctrl@4170000 {
 			reg = <0x0 0x04170000 0x0 0x1000>;
 		};
 
+		fch_dmac: dma-controller@4190000 {
+			compatible = "arm,dma-350";
+			reg = <0x0 0x4190000 0x0 0x10000>;
+			interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>;
+			#dma-cells = <1>;
+		};
+
 		mbox_ap2se: mailbox@5060000 {
 			compatible = "cix,sky1-mbox";
 			reg = <0x0 0x05060000 0x0 0x10000>;
-- 
2.34.1